From 944c858f70ee807f057bc0a6daffc14450e65716 Mon Sep 17 00:00:00 2001
From: Hugo LE BLEVEC <hlebleve@amd.com>
Date: Thu, 4 Aug 2022 10:07:00 +0100
Subject: [PATCH] [Floorplan] Hot fix to correct issues in VitisBuild when
using multiple axilite interfaces.
---
src/finn/transformation/fpgadataflow/floorplan.py | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py
index 564de40db..c3a0567e3 100644
--- a/src/finn/transformation/fpgadataflow/floorplan.py
+++ b/src/finn/transformation/fpgadataflow/floorplan.py
@@ -165,14 +165,15 @@ class Floorplan(Transformation):
for pre_node in pre_nodes:
pre_inst = getCustomOp(pre_node)
pre_slr = pre_inst.get_nodeattr("slr")
- axilite_intf_name = node_inst.get_verilog_top_module_intf_names()["axilite"]
if node_slr == pre_slr:
- if len(axilite_intf_name) != '0':
+ axilite_intf_name = pre_inst.get_verilog_top_module_intf_names()["axilite"]
+ if len(axilite_intf_name) != 0:
node_inst.set_nodeattr("partition_id", partition_cnt)
partition_cnt += 1
else:
partition_id = pre_inst.get_nodeattr("partition_id")
node_inst.set_nodeattr("partition_id", partition_id)
+ break
else:
--
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