From 925e051ff67becf759c6b0c4b0df5c55db60b66a Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Wed, 12 Feb 2020 10:18:22 +0000
Subject: [PATCH] [Test] Changed fpga to PYNQ-Z1
---
tests/fpgadataflow/test_fpgadataflow_ip_stitch.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index 5d7d41a23..0a8e3b0aa 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -22,12 +22,12 @@ from finn.util.basic import (
# TODO control board/part for tests from a global place
# settings for Ultra96
-test_fpga_part = "xczu3eg-sbva484-1-e"
-test_pynq_board = "Ultra96"
+#test_fpga_part = "xczu3eg-sbva484-1-e"
+#test_pynq_board = "Ultra96"
# settings for PYNQ-Z1
-# test_fpga_part = "xc7z020clg400-1"
-# test_pynq_board = "Pynq-Z1"
+test_fpga_part = "xc7z020clg400-1"
+test_pynq_board = "Pynq-Z1"
ip_stitch_model_dir = make_build_dir("test_fpgadataflow_ipstitch")
--
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