From 8d3bde7a10b05028c206da64a09f6b340ca29ff4 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Fri, 17 Jul 2020 14:31:53 +0100
Subject: [PATCH] [Test] add vitis marker to test_fpgadataflow_ipstitch_vitis
---
tests/fpgadataflow/test_fpgadataflow_ipstitch.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
index 411897693..1add41861 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
@@ -426,6 +426,7 @@ def test_fpgadataflow_ipstitch_iodma_floorplan():
@pytest.mark.parametrize("extw", [True, False])
@pytest.mark.slow
@pytest.mark.vivado
+@pytest.mark.vitis
def test_fpgadataflow_ipstitch_vitis(board, period_ns, extw):
platform = alveo_default_platform[board]
fpga_part = alveo_part_map[board]
--
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