From 8bc9f8191d0661b1ffb8b9ffef7473dc89e2eae5 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 10 Jun 2020 23:18:41 +0100
Subject: [PATCH] [Test] fix expected rtlsim cycle counts in end2end_tfc_w1a1
---
tests/end2end/test_end2end_tfc_w1a1.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/end2end/test_end2end_tfc_w1a1.py b/tests/end2end/test_end2end_tfc_w1a1.py
index f9bd408eb..ebfed5e57 100644
--- a/tests/end2end/test_end2end_tfc_w1a1.py
+++ b/tests/end2end/test_end2end_tfc_w1a1.py
@@ -234,11 +234,11 @@ def test_end2end_tfc_w1a1_throughput_test_rtlsim():
# run through IP-stitched rtlsim with increasing batch sizes and
# check the number of cycles it takes to execute
ret = throughput_test_rtlsim(model, 1)
- assert ret["cycles"] == 206
+ assert ret["cycles"] == 205
ret = throughput_test_rtlsim(model, 10)
- assert ret["cycles"] == 845
+ assert ret["cycles"] == 844
ret = throughput_test_rtlsim(model, 100)
- assert ret["cycles"] == 71135
+ assert ret["cycles"] == 7234
@pytest.mark.vivado
--
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