From 882b97a40e72d0532b6b82a6d98ecf2689bfd52f Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Thu, 18 Feb 2021 00:10:36 +0000
Subject: [PATCH] [Notebook] FPGA'21tutorial-specific updates to cybsec
notebook 3
---
.../3-build-accelerator-with-finn.ipynb | 198 +++++++-----------
1 file changed, 77 insertions(+), 121 deletions(-)
diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
index 4bbd75c09..dec9b7b40 100644
--- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
+++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
@@ -6,6 +6,8 @@
"source": [
"# Building the Streaming Dataflow Accelerator\n",
"\n",
+ "<font color=\"red\">**FPGA'21 tutorial:** We recommend clicking Cell -> Run All when you start reading this notebook for \"latency hiding\".</font>\n",
+ "\n",
"**Important: This notebook depends on the 2-cybersecurity-finn-verification notebook because we are using models that were created by these notebooks. So please make sure the needed .onnx files are generated prior to running this notebook.**\n",
"\n",
"<img align=\"left\" src=\"finn-example.png\" alt=\"drawing\" style=\"margin-right: 20px\" width=\"250\"/>\n",
@@ -111,7 +113,7 @@
"output_type": "stream",
"text": [
"Building dataflow accelerator from cybsec-mlp-verified.onnx\n",
- "Intermediate outputs will be generated in /tmp/finn_dev_osboxes\n",
+ "Intermediate outputs will be generated in /tmp/finn_dev_ubuntu\n",
"Final outputs will be generated in output_estimates_only\n",
"Build log is at output_estimates_only/build_dataflow.log\n",
"Running step: step_tidy_up [1/7]\n",
@@ -343,37 +345,44 @@
"\n",
"Once we have a configuration that gives satisfactory estimates, we can move on to generating the accelerator. We can do this in different ways depending on how we want to integrate the accelerator into a larger system. For instance, if we have a larger streaming system built in Vivado or if we'd like to re-use this generated accelerator as an IP component in other projects, the `STITCHED_IP` output product is a good choice. We can also use the `OOC_SYNTH` output product to get post-synthesis resource and clock frequency numbers for our accelerator.\n",
"\n",
- "**NOTE: These next builds will take several minutes since multiple calls to Vivado and a call to the RTL simulator are involved.**"
+ "<font color=\"red\">**FPGA'21 tutorial:** These next builds will take about 10 minutes to complete since multiple calls to Vivado and a call to RTL simulation are involved. \n",
+ " \n",
+ "However, once the `step_create_stitched_ip [11/16]` below is completed, you can view the generated stitched IP in Vivado (over noVNC) while waiting for the rest of the steps to finish. \n",
+ " \n",
+ "noVNC is running on (your AWS URL):6080/vnc.html\n",
+ "</font> "
]
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": 8,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
+ "Previous run results deleted!\n",
"Building dataflow accelerator from cybsec-mlp-verified.onnx\n",
- "Intermediate outputs will be generated in /tmp/finn_dev_osboxes\n",
+ "Intermediate outputs will be generated in /tmp/finn_dev_ubuntu\n",
"Final outputs will be generated in output_ipstitch_ooc_rtlsim\n",
"Build log is at output_ipstitch_ooc_rtlsim/build_dataflow.log\n",
- "Running step: step_tidy_up [1/15]\n",
- "Running step: step_streamline [2/15]\n",
- "Running step: step_convert_to_hls [3/15]\n",
- "Running step: step_create_dataflow_partition [4/15]\n",
- "Running step: step_target_fps_parallelization [5/15]\n",
- "Running step: step_apply_folding_config [6/15]\n",
- "Running step: step_generate_estimate_reports [7/15]\n",
- "Running step: step_hls_ipgen [8/15]\n",
- "Running step: step_set_fifo_depths [9/15]\n",
- "Running step: step_create_stitched_ip [10/15]\n",
- "Running step: step_measure_rtlsim_performance [11/15]\n",
- "Running step: step_make_pynq_driver [12/15]\n",
- "Running step: step_out_of_context_synthesis [13/15]\n",
- "Running step: step_synthesize_bitfile [14/15]\n",
- "Running step: step_deployment_package [15/15]\n",
+ "Running step: step_tidy_up [1/16]\n",
+ "Running step: step_streamline [2/16]\n",
+ "Running step: step_convert_to_hls [3/16]\n",
+ "Running step: step_create_dataflow_partition [4/16]\n",
+ "Running step: step_target_fps_parallelization [5/16]\n",
+ "Running step: step_apply_folding_config [6/16]\n",
+ "Running step: step_generate_estimate_reports [7/16]\n",
+ "Running step: step_hls_codegen [8/16]\n",
+ "Running step: step_hls_ipgen [9/16]\n",
+ "Running step: step_set_fifo_depths [10/16]\n",
+ "Running step: step_create_stitched_ip [11/16]\n",
+ "Running step: step_measure_rtlsim_performance [12/16]\n",
+ "Running step: step_make_pynq_driver [13/16]\n",
+ "Running step: step_out_of_context_synthesis [14/16]\n",
+ "Running step: step_synthesize_bitfile [15/16]\n",
+ "Running step: step_deployment_package [16/16]\n",
"Completed successfully\n"
]
},
@@ -383,7 +392,7 @@
"0"
]
},
- "execution_count": 2,
+ "execution_count": 8,
"metadata": {},
"output_type": "execute_result"
}
@@ -427,19 +436,19 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": 9,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "all_verilog_srcs.txt\t\t finn_vivado_stitch_proj.xpr\r\n",
- "finn_vivado_stitch_proj.cache\t ip\r\n",
- "finn_vivado_stitch_proj.hbs\t make_project.sh\r\n",
+ "all_verilog_srcs.txt\t\t ip\r\n",
+ "finn_vivado_stitch_proj.cache\t make_project.sh\r\n",
"finn_vivado_stitch_proj.hw\t make_project.tcl\r\n",
"finn_vivado_stitch_proj.ip_user_files vivado.jou\r\n",
- "finn_vivado_stitch_proj.srcs\t vivado.log\r\n"
+ "finn_vivado_stitch_proj.srcs\t vivado.log\r\n",
+ "finn_vivado_stitch_proj.xpr\r\n"
]
}
],
@@ -456,7 +465,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": 10,
"metadata": {},
"outputs": [
{
@@ -481,7 +490,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": 11,
"metadata": {},
"outputs": [
{
@@ -489,15 +498,15 @@
"output_type": "stream",
"text": [
"{\r\n",
- " \"vivado_proj_folder\": \"/tmp/finn_dev_osboxes/synth_out_of_context_wy3b6qf4/results_finn_design_wrapper\",\r\n",
- " \"LUT\": 7073.0,\r\n",
- " \"FF\": 7534.0,\r\n",
+ " \"vivado_proj_folder\": \"/tmp/finn_dev_ubuntu/synth_out_of_context_8u74_j7t/results_finn_design_wrapper\",\r\n",
+ " \"LUT\": 7931.0,\r\n",
+ " \"FF\": 7319.0,\r\n",
" \"DSP\": 0.0,\r\n",
" \"BRAM\": 18.0,\r\n",
- " \"WNS\": 0.632,\r\n",
+ " \"WNS\": 1.562,\r\n",
" \"\": 0,\r\n",
- " \"fmax_mhz\": 106.7463706233988,\r\n",
- " \"estimated_throughput_fps\": 1334329.6327924852\r\n",
+ " \"fmax_mhz\": 118.51149561507465,\r\n",
+ " \"estimated_throughput_fps\": 1481393.6951884332\r\n",
"}"
]
}
@@ -515,7 +524,7 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": 12,
"metadata": {},
"outputs": [
{
@@ -523,14 +532,14 @@
"output_type": "stream",
"text": [
"{\r\n",
- " \"cycles\": 838,\r\n",
- " \"runtime[ms]\": 0.00838,\r\n",
- " \"throughput[images/s]\": 954653.9379474939,\r\n",
- " \"DRAM_in_bandwidth[Mb/s]\": 71.59904534606204,\r\n",
- " \"DRAM_out_bandwidth[Mb/s]\": 0.11933174224343673,\r\n",
+ " \"cycles\": 840,\r\n",
+ " \"runtime[ms]\": 0.008400000000000001,\r\n",
+ " \"throughput[images/s]\": 952380.9523809523,\r\n",
+ " \"DRAM_in_bandwidth[Mb/s]\": 71.42857142857142,\r\n",
+ " \"DRAM_out_bandwidth[Mb/s]\": 0.11904761904761903,\r\n",
" \"fclk[mhz]\": 100.0,\r\n",
" \"N\": 8,\r\n",
- " \"latency_cycles\": 229\r\n",
+ " \"latency_cycles\": 231\r\n",
"}"
]
}
@@ -548,7 +557,7 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": 13,
"metadata": {},
"outputs": [
{
@@ -615,49 +624,22 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "## Launch a Build: PYNQ Bitfile and Driver <a id=\"build_bitfile_driver\"></a>"
+ "## (Optional) Launch a Build: PYNQ Bitfile and Driver <a id=\"build_bitfile_driver\"></a>\n",
+ "\n",
+ "<font color=\"red\">**FPGA'21 tutorial:** This section is not included in the hands-on tutorial due to the bitfile synthesis time (15-20 min). We encourage you to uncomment the cells below to try it out on your own after the tutorial.</font>"
]
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": 14,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "Building dataflow accelerator from cybsec-mlp-verified.onnx\n",
- "Intermediate outputs will be generated in /tmp/finn_dev_osboxes\n",
- "Final outputs will be generated in output_final\n",
- "Build log is at output_final/build_dataflow.log\n",
- "Running step: step_tidy_up [1/15]\n",
- "Running step: step_streamline [2/15]\n",
- "Running step: step_convert_to_hls [3/15]\n",
- "Running step: step_create_dataflow_partition [4/15]\n",
- "Running step: step_target_fps_parallelization [5/15]\n",
- "Running step: step_apply_folding_config [6/15]\n",
- "Running step: step_generate_estimate_reports [7/15]\n",
- "Running step: step_hls_ipgen [8/15]\n",
- "Running step: step_set_fifo_depths [9/15]\n",
- "Running step: step_create_stitched_ip [10/15]\n",
- "Running step: step_measure_rtlsim_performance [11/15]\n",
- "Running step: step_make_pynq_driver [12/15]\n",
- "Running step: step_out_of_context_synthesis [13/15]\n",
- "Running step: step_synthesize_bitfile [14/15]\n",
- "Running step: step_deployment_package [15/15]\n",
- "Completed successfully\n"
+ "Previous run results deleted!\n"
]
- },
- {
- "data": {
- "text/plain": [
- "0"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
}
],
"source": [
@@ -684,9 +666,16 @@
" build_cfg.DataflowOutputType.PYNQ_DRIVER,\n",
" build_cfg.DataflowOutputType.DEPLOYMENT_PACKAGE,\n",
" ]\n",
- ")\n",
- "\n",
- "build.build_dataflow_cfg(model_file, cfg)"
+ ")"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#build.build_dataflow_cfg(model_file, cfg)"
]
},
{
@@ -698,19 +687,11 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": 16,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "finn-accel.bit\tfinn-accel.hwh\r\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
- "! ls {final_output_dir}/bitfile"
+ "#! ls {final_output_dir}/bitfile"
]
},
{
@@ -722,19 +703,11 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": 17,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "driver.py driver_base.py finn runtime_weights validate.py\r\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
- "! ls {final_output_dir}/driver"
+ "#! ls {final_output_dir}/driver"
]
},
{
@@ -746,20 +719,11 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": 18,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "estimate_layer_resources_hls.json post_synth_resources.xml\r\n",
- "post_route_timing.rpt\r\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
- "! ls {final_output_dir}/report"
+ "#! ls {final_output_dir}/report"
]
},
{
@@ -771,19 +735,11 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": 19,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "bitfile driver\r\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
- "! ls {final_output_dir}/deploy"
+ "#! ls {final_output_dir}/deploy"
]
},
{
--
GitLab