diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index c22a21ebdfd19178d3937de3a235dfadb7ee1d71..df9700d7101693e2604aeb6075daa1981cec56a0 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -48,9 +48,10 @@ class CreateStitchedIP(Transformation):
     The packaged block design IP can be found under the ip subdirectory.
     """
 
-    def __init__(self, fpgapart):
+    def __init__(self, fpgapart, fclk_mhz):
         super().__init__()
         self.fpgapart = fpgapart
+        self.fclk_mhz = fclk_mhz
 
     def apply(self, model):
         ip_dirs = ["list"]
@@ -147,8 +148,8 @@ class CreateStitchedIP(Transformation):
         tcl.append('create_bd_design "%s"' % block_name)
         tcl.extend(create_cmds)
         tcl.extend(connect_cmds)
-        # TODO get from Transformation arg or metadata_prop
-        fclk_hz = 100 * 1000000
+        fclk_hz = self.fclk_mhz * 1000000
+        model.set_metadata_prop("fclk_MHz", str(self.fclk_mhz))
         tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
         tcl.append("regenerate_bd_layout")
         tcl.append("validate_bd_design")
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 429b74bb5ea7e359ea720a0a86706f2c653ee6ce..4a0ab71216a1c89f98254ac2d8f989dcb830e3a6 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -110,8 +110,6 @@ class MakePYNQProject(Transformation):
         nrst_name = "ap_rst_n_0"
         axi_lite_if_name = "s_axi_control_0"
         vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
-        # TODO get from Transformation arg or metadata_prop
-        fclk_mhz = 100.0
 
         # create a temporary folder for the project
         vivado_pynq_proj_dir = make_build_dir(prefix="vivado_pynq_proj_")
@@ -120,6 +118,9 @@ class MakePYNQProject(Transformation):
         synth_report_filename = vivado_pynq_proj_dir + "/synth_report.xml"
         model.set_metadata_prop("vivado_synth_rpt", synth_report_filename)
 
+        # get metadata property for clock frequency
+        fclk_mhz = float(model.get_metadata_prop("fclk_MHz"))
+
         ip_config_tcl = templates.ip_config_tcl_template % (
             vivado_pynq_proj_dir,
             ip_dirs_str,
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index b5f3f4e27ff24723db69f887cb7f1cce9c4df617..6303990a1b7f208acac6c3d9e24acf78ab157d00 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -78,7 +78,7 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
 build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
 test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
 test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 10
+target_clk_ns = 5
 mem_mode = "decoupled"
 
 
@@ -164,7 +164,8 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
 def test_end2end_tfc_w1a1_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    fclk_MHz = 1 / (target_clk_ns * 0.001)
+    model = model.transform(CreateStitchedIP(test_fpga_part, fclk_MHz))
     model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")