From 7a5146c4aa415aee84f6eceedec676102fdf7dfe Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Fri, 12 Nov 2021 21:31:42 +0100
Subject: [PATCH] [Concat] make both cppsim and rtl/stitched-ip rtlsim work
---
src/finn/custom_op/fpgadataflow/concat.py | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py
index c591cdec6..3d61d3abc 100644
--- a/src/finn/custom_op/fpgadataflow/concat.py
+++ b/src/finn/custom_op/fpgadataflow/concat.py
@@ -150,7 +150,14 @@ class StreamingConcat(HLSCustomOp):
impl_hls_code.append("for(unsigned int i = 0; i < numReps; i++) {")
impl_hls_code.append("#pragma HLS PIPELINE II=1")
impl_hls_code.append("ap_uint<%d> out_elem;" % total_bw)
+ # FIXME: the order of streams for concatenation works out differently
+ # for cppsim vs rtlsim, addressed via reversing the order of commands
+ # for now
+ impl_hls_code.append("#ifdef __SYNTHESIS__")
+ impl_hls_code.append("out_elem = (" + ",".join(commands[::-1]) + ");")
+ impl_hls_code.append("#else")
impl_hls_code.append("out_elem = (" + ",".join(commands) + ");")
+ impl_hls_code.append("#endif")
impl_hls_code.append("out.write(out_elem);")
impl_hls_code.append("}")
impl_hls_code.append("}")
@@ -211,7 +218,7 @@ class StreamingConcat(HLSCustomOp):
"%s/input_%d.npy" % (code_gen_dir, i),
export_idt,
nbits,
- reverse_inner=False,
+ reverse_inner=True,
)
io_dict["inputs"]["in%d" % i] = rtlsim_inp
super().reset_rtlsim(sim)
@@ -231,7 +238,7 @@ class StreamingConcat(HLSCustomOp):
out_shape,
packed_bits,
target_bits,
- reverse_inner=False,
+ reverse_inner=True,
)
# load and reshape output
output = np.load(out_npy_path)
--
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