diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index 5de97fd976f8d57c7c389c04ad33e02340f13e56..2500b1f03b917225d92b00de033299f20e3d9f5d 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -31,7 +31,7 @@ import numpy as np
 import os
 import subprocess
 from finn.custom_op import CustomOp
-from finn.util.basic import CppBuilder
+from finn.util.basic import CppBuilder, make_build_dir
 from finn.util.fpgadataflow import (
     IPGenBuilder,
     pyverilate_get_liveness_threshold_cycles,
@@ -119,6 +119,7 @@ class HLSCustomOp(CustomOp):
         # build the Verilator emu library
         sim = PyVerilator.build(
             verilog_file,
+            build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"),
             verilog_path=[
                 "{}/project_{}/sol1/impl/verilog/".format(
                     code_gen_dir, self.onnx_node.name
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index 5b29ddbcd1dcc4f771dbc4eb633bf7c1ecb6b3aa..e84532d8d24909cc5add09fbc623a13c955ffb72 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -33,7 +33,7 @@ try:
     from pyverilator import PyVerilator
 except ModuleNotFoundError:
     PyVerilator = None
-from finn.util.basic import get_by_name
+from finn.util.basic import get_by_name, make_build_dir
 
 
 class IPGenBuilder:
@@ -85,7 +85,10 @@ def pyverilate_stitched_ip(model):
 
     all_verilog_dirs = list(map(file_to_dir, all_verilog_srcs))
     top_verilog = model.get_metadata_prop("wrapper_filename")
-    sim = PyVerilator.build(top_verilog, verilog_path=all_verilog_dirs)
+    build_dir = make_build_dir("pyverilator_ipstitched_")
+    sim = PyVerilator.build(
+        top_verilog, verilog_path=all_verilog_dirs, build_dir=build_dir
+    )
     return sim