From 7604d45abe0051b44694d6c5ab8ca5092af2b601 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Tue, 13 Oct 2020 22:04:57 +0200
Subject: [PATCH] [Build] restrict to single AXI-lite, get interface name from
attr
---
.../fpgadataflow/make_zynq_proj.py | 14 ++++++--
.../fpgadataflow/vitis_build.py | 36 ++++++++++++++-----
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 1a4b67d1e..3c980a45e 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -136,6 +136,15 @@ class MakeZYNQProject(Transformation):
if clk_ns > global_clk_ns:
global_clk_ns = clk_ns
+ ifnames = eval(kernel_model.set_metadata_prop("vivado_stitch_ifnames"))
+ assert (
+ len(ifnames["axilite"]) <= 1
+ ), "MakeZYNQProject supports max 1 AXI lite interface"
+ if len(ifnames["axilite"]) == 1:
+ axilite_intf_name = ifnames["axilite"][0]
+ else:
+ axilite_intf_name = None
+
# gather info on connectivity
# assume each node connected to outputs/inputs is DMA:
# has axis, aximm and axilite
@@ -162,10 +171,11 @@ class MakeZYNQProject(Transformation):
"[get_bd_intf_pins smartconnect_0/S%02d_AXI]"
% (instance_names[node.name], aximm_idx)
)
+ assert axilite_intf_name is not None
config.append(
- "connect_bd_intf_net [get_bd_intf_pins %s/s_axi_control] "
+ "connect_bd_intf_net [get_bd_intf_pins %s/%s] "
"[get_bd_intf_pins axi_interconnect_0/M%02d_AXI]"
- % (instance_names[node.name], axilite_idx)
+ % (axilite_intf_name, instance_names[node.name], axilite_idx)
)
idma_idx += 1
aximm_idx += 1
diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py
index b6fc62f57..d4d143421 100644
--- a/src/finn/transformation/fpgadataflow/vitis_build.py
+++ b/src/finn/transformation/fpgadataflow/vitis_build.py
@@ -95,6 +95,15 @@ class CreateVitisXO(Transformation):
# NOTE: this assumes the graph is Vitis-compatible: max one axi lite interface
# developed from instructions in UG1393 (v2019.2) and package_xo documentation
# package_xo is responsible for generating the kernel xml
+ ifnames = eval(model.set_metadata_prop("vivado_stitch_ifnames"))
+ assert (
+ len(ifnames["axilite"]) <= 1
+ ), "CreateVitisXO supports max 1 AXI lite interface"
+ if len(ifnames["axilite"]) == 1:
+ axilite_intf_name = ifnames["axilite"][0]
+ else:
+ axilite_intf_name = None
+
for node in model.graph.node:
node_inst = getCustomOp(node)
arg_id = 0
@@ -117,8 +126,10 @@ class CreateVitisXO(Transformation):
# add a axilite port if dynamic
# add a count parameter if dynamic
if node_inst.get_nodeattr("DynIters") == 1:
+ assert axilite_intf_name is not None
args_string.append(
- "{numReps:0:%s:s_axi_control:0x4:0x10:uint:0}" % str(arg_id)
+ "{numReps:0:%s:%s:0x4:0x10:uint:0}"
+ % (str(arg_id), axilite_intf_name)
)
arg_id += 1
elif node.op_type == "IODMA":
@@ -131,7 +142,8 @@ class CreateVitisXO(Transformation):
)
arg_id += 1
args_string.append(
- "{numReps:0:%s:s_axi_control:0x4:0x1C:uint:0}" % str(arg_id)
+ "{numReps:0:%s:%s:0x4:0x1C:uint:0}"
+ % (str(arg_id), axilite_intf_name)
)
arg_id += 1
@@ -175,8 +187,11 @@ class VitisLink(Transformation):
"""
def __init__(
- self, platform, f_mhz=200, strategy=VitisOptStrategy.PERFORMANCE,
- enable_debug=False
+ self,
+ platform,
+ f_mhz=200,
+ strategy=VitisOptStrategy.PERFORMANCE,
+ enable_debug=False,
):
super().__init__()
self.platform = platform
@@ -316,9 +331,12 @@ class VitisBuild(Transformation):
"""Best-effort attempt at building the accelerator with Vitis."""
def __init__(
- self, fpga_part, period_ns, platform,
+ self,
+ fpga_part,
+ period_ns,
+ platform,
strategy=VitisOptStrategy.PERFORMANCE,
- enable_debug=False
+ enable_debug=False,
):
super().__init__()
self.fpga_part = fpga_part
@@ -372,8 +390,10 @@ class VitisBuild(Transformation):
# Assemble design from kernels
model = model.transform(
VitisLink(
- self.platform, round(1000 / self.period_ns), strategy=self.strategy,
- enable_debug=self.enable_debug
+ self.platform,
+ round(1000 / self.period_ns),
+ strategy=self.strategy,
+ enable_debug=self.enable_debug,
)
)
# set platform attribute for correct remote execution
--
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