diff --git a/finn-rtllib/swg/swg_template_wrapper_dynamic.v b/finn-rtllib/swg/swg_template_wrapper_dynamic.v
index d6f839de43c3c13c6d1a9a772b21d976e2348a08..8d16dc10bb8a0c5fd8878ac11224b88a0242b6ad 100644
--- a/finn-rtllib/swg/swg_template_wrapper_dynamic.v
+++ b/finn-rtllib/swg/swg_template_wrapper_dynamic.v
@@ -14,13 +14,13 @@ module $TOP_MODULE_NAME$ #(
parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN,
parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT,
- parameter integer C_s_axi_cfg_DATA_WIDTH = 32,
- parameter integer C_s_axi_cfg_ADDR_WIDTH = 6
+ parameter integer C_s_axilite_DATA_WIDTH = 32,
+ parameter integer C_s_axilite_ADDR_WIDTH = 6
)
(
- (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axi_cfg" *)
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
input ap_clk,
- (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axi_cfg" *)
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
input ap_rst_n,
input [BUF_IN_WIDTH-1:0] in0_V_TDATA,
input in0_V_TVALID,
@@ -29,28 +29,28 @@ module $TOP_MODULE_NAME$ #(
output out_V_TVALID,
input out_V_TREADY,
- // Ports of Axi Slave Bus Interface s_axi_cfg
- //input wire s_axi_cfg_aclk,
- //input wire s_axi_cfg_aresetn,
- input wire [C_s_axi_cfg_ADDR_WIDTH-1 : 0] s_axi_cfg_awaddr,
- input wire [2 : 0] s_axi_cfg_awprot,
- input wire s_axi_cfg_awvalid,
- output wire s_axi_cfg_awready,
- input wire [C_s_axi_cfg_DATA_WIDTH-1 : 0] s_axi_cfg_wdata,
- input wire [(C_s_axi_cfg_DATA_WIDTH/8)-1 : 0] s_axi_cfg_wstrb,
- input wire s_axi_cfg_wvalid,
- output wire s_axi_cfg_wready,
- output wire [1 : 0] s_axi_cfg_bresp,
- output wire s_axi_cfg_bvalid,
- input wire s_axi_cfg_bready,
- input wire [C_s_axi_cfg_ADDR_WIDTH-1 : 0] s_axi_cfg_araddr,
- input wire [2 : 0] s_axi_cfg_arprot,
- input wire s_axi_cfg_arvalid,
- output wire s_axi_cfg_arready,
- output wire [C_s_axi_cfg_DATA_WIDTH-1 : 0] s_axi_cfg_rdata,
- output wire [1 : 0] s_axi_cfg_rresp,
- output wire s_axi_cfg_rvalid,
- input wire s_axi_cfg_rready
+ // Ports of Axi Slave Bus Interface s_axilite
+ //input wire s_axilite_aclk,
+ //input wire s_axilite_aresetn,
+ input wire [C_s_axilite_ADDR_WIDTH-1 : 0] s_axilite_awaddr,
+ input wire [2 : 0] s_axilite_awprot,
+ input wire s_axilite_awvalid,
+ output wire s_axilite_awready,
+ input wire [C_s_axilite_DATA_WIDTH-1 : 0] s_axilite_wdata,
+ input wire [(C_s_axilite_DATA_WIDTH/8)-1 : 0] s_axilite_wstrb,
+ input wire s_axilite_wvalid,
+ output wire s_axilite_wready,
+ output wire [1 : 0] s_axilite_bresp,
+ output wire s_axilite_bvalid,
+ input wire s_axilite_bready,
+ input wire [C_s_axilite_ADDR_WIDTH-1 : 0] s_axilite_araddr,
+ input wire [2 : 0] s_axilite_arprot,
+ input wire s_axilite_arvalid,
+ output wire s_axilite_arready,
+ output wire [C_s_axilite_DATA_WIDTH-1 : 0] s_axilite_rdata,
+ output wire [1 : 0] s_axilite_rresp,
+ output wire s_axilite_rvalid,
+ input wire s_axilite_rready
);
wire cfg_valid;
@@ -70,32 +70,32 @@ wire [INCR_BITWIDTH-1:0] cfg_incr_tail_last;
wire [31:0] cfg_last_read;
wire [31:0] cfg_last_write;
-// Instantiation of Axi Bus Interface s_axi_cfg
+// Instantiation of Axi Bus Interface s_axilite
$TOP_MODULE_NAME$_axilite # (
- .C_S_AXI_DATA_WIDTH(C_s_axi_cfg_DATA_WIDTH),
- .C_S_AXI_ADDR_WIDTH(C_s_axi_cfg_ADDR_WIDTH)
+ .C_S_AXI_DATA_WIDTH(C_s_axilite_DATA_WIDTH),
+ .C_S_AXI_ADDR_WIDTH(C_s_axilite_ADDR_WIDTH)
) axilite_cfg_inst (
.S_AXI_ACLK(ap_clk),
.S_AXI_ARESETN(ap_rst_n),
- .S_AXI_AWADDR(s_axi_cfg_awaddr),
- .S_AXI_AWPROT(s_axi_cfg_awprot),
- .S_AXI_AWVALID(s_axi_cfg_awvalid),
- .S_AXI_AWREADY(s_axi_cfg_awready),
- .S_AXI_WDATA(s_axi_cfg_wdata),
- .S_AXI_WSTRB(s_axi_cfg_wstrb),
- .S_AXI_WVALID(s_axi_cfg_wvalid),
- .S_AXI_WREADY(s_axi_cfg_wready),
- .S_AXI_BRESP(s_axi_cfg_bresp),
- .S_AXI_BVALID(s_axi_cfg_bvalid),
- .S_AXI_BREADY(s_axi_cfg_bready),
- .S_AXI_ARADDR(s_axi_cfg_araddr),
- .S_AXI_ARPROT(s_axi_cfg_arprot),
- .S_AXI_ARVALID(s_axi_cfg_arvalid),
- .S_AXI_ARREADY(s_axi_cfg_arready),
- .S_AXI_RDATA(s_axi_cfg_rdata),
- .S_AXI_RRESP(s_axi_cfg_rresp),
- .S_AXI_RVALID(s_axi_cfg_rvalid),
- .S_AXI_RREADY(s_axi_cfg_rready),
+ .S_AXI_AWADDR(s_axilite_awaddr),
+ .S_AXI_AWPROT(s_axilite_awprot),
+ .S_AXI_AWVALID(s_axilite_awvalid),
+ .S_AXI_AWREADY(s_axilite_awready),
+ .S_AXI_WDATA(s_axilite_wdata),
+ .S_AXI_WSTRB(s_axilite_wstrb),
+ .S_AXI_WVALID(s_axilite_wvalid),
+ .S_AXI_WREADY(s_axilite_wready),
+ .S_AXI_BRESP(s_axilite_bresp),
+ .S_AXI_BVALID(s_axilite_bvalid),
+ .S_AXI_BREADY(s_axilite_bready),
+ .S_AXI_ARADDR(s_axilite_araddr),
+ .S_AXI_ARPROT(s_axilite_arprot),
+ .S_AXI_ARVALID(s_axilite_arvalid),
+ .S_AXI_ARREADY(s_axilite_arready),
+ .S_AXI_RDATA(s_axilite_rdata),
+ .S_AXI_RRESP(s_axilite_rresp),
+ .S_AXI_RVALID(s_axilite_rvalid),
+ .S_AXI_RREADY(s_axilite_rready),
.cfg_reg0(cfg_valid),
.cfg_reg1(cfg_cntr_simd),
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
index 665325bdee56d7de5936fb544f744c0341358387..77a3d189744efc39940c2f57b1c6b65da2c70a25 100755
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
@@ -844,7 +844,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
Each block must have at most one aximm and one axilite."""
intf_names = super().get_verilog_top_module_intf_names()
if self.get_nodeattr("dynamic_mode"):
- intf_names["axilite"] = ["s_axi_cfg"]
+ intf_names["axilite"] = ["s_axilite"]
return intf_names
def get_dynamic_config(self, ifm_dim, stride=None, dilation=None):
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
index 0db3c139fb0f9b7fb34f06c09e700fa322a7f823..36204de35964de6f7d9e3537f354ba54536dfa86 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
@@ -155,8 +155,8 @@ def config_hook(configs):
for config_entry in config.values():
axilite_write(sim, config_entry[0], config_entry[1], basename=axi_name)
# 2. Set cfg_valid flag (>= 1 cycle) for SWGG
- # TODO better interface names to separate SWGG and padding
- if "s_axi_cfg" in axi_name:
+ # TODO direct add wren register to generated config?
+ if len(config) == 15:
axilite_write(sim, 0, 1, basename=axi_name)
# 3. Reset component (>= 1 cycle)
reset_rtlsim(sim)
@@ -215,8 +215,8 @@ def test_fpgadataflow_conv_dynamic(pad_mode):
for swg_node in dyn_nodes:
getCustomOp(swg_node).set_nodeattr("SIMD", 1)
getCustomOp(swg_node).set_nodeattr("dynamic_mode", 1)
- getCustomOp(swg_node).set_nodeattr("inFIFODepth", 16)
- getCustomOp(swg_node).set_nodeattr("outFIFODepth", 16)
+ getCustomOp(swg_node).set_nodeattr("inFIFODepths", [16])
+ getCustomOp(swg_node).set_nodeattr("outFIFODepths", [16])
model = model.transform(InsertFIFO())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
@@ -235,12 +235,11 @@ def test_fpgadataflow_conv_dynamic(pad_mode):
swg0 = getCustomOp(swg_nodes[0])
update_tensor_dim(model, swg0.onnx_node.input[0], (conv0_idim, conv0_idim))
update_tensor_dim(model, swg0.onnx_node.output[0], (int_dim, int_dim))
- config0 = swg0.get_dynamic_config((conv0_idim, conv0_idim))
+ swg_config0 = swg0.get_dynamic_config((conv0_idim, conv0_idim))
swg1 = getCustomOp(swg_nodes[1])
update_tensor_dim(model, swg1.onnx_node.input[0], (conv1_idim, conv1_idim))
update_tensor_dim(model, swg1.onnx_node.output[0], (odim, odim))
- config1 = swg1.get_dynamic_config((conv1_idim, conv1_idim))
- configs = [("s_axi_cfg_0_", config0), ("s_axi_cfg_1_", config1)]
+ swg_config1 = swg1.get_dynamic_config((conv1_idim, conv1_idim))
if pad_mode != "VALID":
pad_nodes = model.get_nodes_by_op_type("FMPadding_rtl")
padder0 = getCustomOp(pad_nodes[0])
@@ -255,8 +254,14 @@ def test_fpgadataflow_conv_dynamic(pad_mode):
model, padder1.onnx_node.output[0], (conv1_idim, conv1_idim)
)
pad_config1 = padder1.get_dynamic_config((int_dim, int_dim), pad1)
- configs.append(("s_axilite_0_", pad_config0))
- configs.append(("s_axilite_1_", pad_config1))
+ configs = [
+ ("s_axilite_0_", pad_config0),
+ ("s_axilite_1_", swg_config0),
+ ("s_axilite_2_", pad_config1),
+ ("s_axilite_3_", swg_config1),
+ ]
+ else:
+ configs = [("s_axilite_0_", swg_config0), ("s_axilite_1_", swg_config1)]
# adjust folded shapes for I/O FIFOs
# (since rtlsim_exec uses folded shape info to fold global i/o tensors)
first_node = getCustomOp(model.graph.node[0])