From 6d0a79c574f49ed21626e7f3af71d8c9c5741087 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 21 Feb 2020 00:56:20 +0000
Subject: [PATCH] [CustomOp] reflect hls prefix changes for rtlsim
---
src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py | 5 +++--
src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py | 3 ++-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index 8ae626f14..1da761871 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -98,9 +98,10 @@ class ConvolutionInputGenerator(HLSCustomOp):
)
elif mode == "rtlsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
- code_gen_dir, node.name, node.name
+ code_gen_dir, node.name, prefixed_top_name
)
if os.path.isfile(verilog_file):
inp = context[node.input[0]]
@@ -209,7 +210,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
self.code_gen_dict["$DOCOMPUTE$"] = [
"""{}<ConvKernelDim1, IFMChannels1, Input_precision1, IFMDim1,
OFMDim1, SIMD1, Stride1> (in0, out, numReps);""".format(
- node.op_type,
+ node.op_type
)
]
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 643a2062d..2dd937fce 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -479,9 +479,10 @@ class StreamingFCLayer_Batch(HLSCustomOp):
# reshape output to have expected shape
context[node.output[0]] = context[node.output[0]].reshape(1, mh)
elif mode == "rtlsim":
+ prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
- code_gen_dir, node.name, node.name
+ code_gen_dir, node.name, prefixed_top_name
)
if os.path.isfile(verilog_file):
nbits = self.get_instream_width()
--
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