diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 75be2bec869959cdd8fc227677f80a5e40c2a56e..37c6ad4894a1a82878f68c92501844d7fd45d353 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -745,7 +745,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
                 )
                 num_w_reps = np.prod(self.get_nodeattr("numInputVectors"))
                 io_dict = {
-                    "inputs": {"in0": inp, "weights": wei*num_w_reps},
+                    "inputs": {"in0": inp, "weights": wei * num_w_reps},
                     "outputs": {"out": []},
                 }
                 self.rtlsim_multi_io(sim, io_dict)
@@ -1126,6 +1126,11 @@ class StreamingFCLayer_Batch(HLSCustomOp):
                 % (node_name, dout_name, node_name, node_name, dout_name)
             )
             cmd.append("save_bd_design")
+        elif mem_mode == "const":
+            # base class impl sufficient for const mode
+            return super().code_generation_ipi()
+        else:
+            raise Exception("Unrecognized mem_mode for StreamingFCLayer")
         return cmd
 
     def get_verilog_top_module_intf_names(self):