From 67af933086c58ed5e74475b43408b22e9873ba51 Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Fri, 13 May 2022 13:41:38 +0200
Subject: [PATCH] Experimental fix for address mapping issues
---
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index b19ef170f..bbe3c60b8 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -363,6 +363,13 @@ class CreateStitchedIP(Transformation):
)
% (vivado_stitch_proj_dir, block_vendor, block_library, block_name)
)
+ # in some cases, the IP packager seems to infer an aperture of 64K or 4G,
+ # preventing address assignment of the DDR_LOW and/or DDR_HIGH segments
+ # the following is a hotfix to remove this aperture during IODMA packaging
+ tcl.append(
+ "ipx::remove_segment -quiet m_axi_gmem0:APERTURE_0 "
+ "[ipx::get_address_spaces m_axi_gmem0 -of_objects [ipx::current_core]]"
+ )
tcl.append("set_property core_revision 2 [ipx::find_open_core %s]" % block_vlnv)
tcl.append("ipx::create_xgui_files [ipx::find_open_core %s]" % block_vlnv)
# mark bus interface params as user-resolvable to avoid FREQ_MHZ mismatches
--
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