From 66a195aaebbd4f9859ca25a316d2a0d8794b7da0 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Fri, 28 Feb 2020 17:14:30 +0000
Subject: [PATCH] [Docs] add links to verification notebook o
---
docs/finn/end_to_end_flow.rst | 13 ++++++-------
docs/finn/tutorials.rst | 3 +++
docs/finn/verification.rst | 6 ++++--
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/docs/finn/end_to_end_flow.rst b/docs/finn/end_to_end_flow.rst
index 855be7e51..1936aad18 100644
--- a/docs/finn/end_to_end_flow.rst
+++ b/docs/finn/end_to_end_flow.rst
@@ -4,23 +4,22 @@ End-to-End Flow
.. note:: **This website is currently under construction.**
-The following image shows the end-to-end flow of FINN. As you can see in the picture, FINN has a high modularity and has the property that the flow can be stopped at any point and the intermediate result can be used for further processing or other purposes. This enables a wide range of users to benefit from FINN, even if they do not use the whole flow.
+The following image shows an example end-to-end flow in FINN, starting from a trained PyTorch/Brevitas network and going all the way to a running FPGA accelerator.
+As you can see in the picture, FINN has a high modularity and has the property that the flow can be stopped at any point and the intermediate result can be used for further processing or other purposes. This enables a wide range of users to benefit from FINN, even if they do not use the whole flow.
.. image:: ../../notebooks/end2end_example/finn-design-flow-example.svg
:scale: 50%
:align: center
-The cylinder-like fields show the state of the network representation in the respective step. The rectangular fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into five blocks, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (pink block), followed by the preparation of the network (grey block) for the Vivado HLS and Vivado IPI (yellow block). There is also a section for testing and verification in software (green block) and the hardware generation and deployment on the PYNQ board (red block).
+The cylinder-like fields show the state of the network representation in the respective step. The rectangular fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into five blocks, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (pink block), followed by the preparation of the network (grey block) for the Vivado HLS and Vivado IPI (yellow block). There is also a section for testing and verification in software (green block) and the hardware generation and deployment on the PYNQ board (red block).
-For more details about the different flow sections, please have a look at the corresponding pages on this website.
+This example flow is covered in the `end2end_example <https://github.com/Xilinx/finn/tree/master/notebooks/end2end_example>`_ Jupyter notebooks.
+For a more detailed overview about the different flow sections, please have a look at the corresponding pages:
.. toctree::
-
+
brevitas_export
nw_prep
vivado_synth
pynq_deploy
verification
-
-
-
diff --git a/docs/finn/tutorials.rst b/docs/finn/tutorials.rst
index cd852d82b..2a234b15e 100644
--- a/docs/finn/tutorials.rst
+++ b/docs/finn/tutorials.rst
@@ -56,3 +56,6 @@ End-to-End Flow
This notebook shows the FINN end-to-end flow step by step using an example of a simple, binarized, fully-connected network trained on the MNIST data set. Starting with the brevitas export and taking this particular network all the way down to hardware by using a specific sequence of transformations.
* `tfc_end2end_example <https://github.com/Xilinx/finn/blob/master/notebooks/end2end_example/tfc_end2end_example.ipynb>`_
+ * This notebook takes the model step-by-step from a trained Brevitas net to a running FPGA bitfile.
+* `tfc_end2end_verification <https://github.com/Xilinx/finn/blob/master/notebooks/end2end_example/tfc_end2end_verification.ipynb>`_
+ * This notebook runs parellel to the tfc_end2end_example notebook above, and shows how the output of each step can be verified.
diff --git a/docs/finn/verification.rst b/docs/finn/verification.rst
index 03e12fd69..13e6fae7a 100644
--- a/docs/finn/verification.rst
+++ b/docs/finn/verification.rst
@@ -10,12 +10,14 @@ Functional Verification
:scale: 70%
:align: center
-When the network is transformed it is important to verify the functionality to make sure the transformation did not change the behaviour of the model. There are multiple ways of verification that can be applied in different stages of the network inside FINN. All can be accessed using the execution function in module :py:mod:`finn.core.onnx_exec`. The execution happens in most cases node by node, which supports networks that have a mixture of standard ONNX nodes, custom nodes and HLS custom nodes. Because the single node can be executed using one of the following methods.
+"* This part of the flow is covered by the `this notebook <https://github.com/Xilinx/finn/tree/master/notebooks/end2end_example/tfc_end2end_verification.ipynb>`_. *"
+
+When the network is transformed it is important to verify the functionality to make sure the transformation did not change the behaviour of the model. There are multiple ways of verification that can be applied in different stages of the network inside FINN. All can be accessed using the execution function in module :py:mod:`finn.core.onnx_exec`. The execution happens in most cases node by node, which supports networks that have a mixture of standard ONNX nodes, custom nodes and HLS custom nodes. A single node can be executed using one or more of the following methods:
Simulation using Python
=======================
-This simulation can be used right after the :ref:`brevitas_export` or when the network does not contain any HLS custom nodes, so right after the streamlining transformations and before the nodes are converted into HLS layers.
+This simulation can be used right after the :ref:`brevitas_export` or when the network does not contain any HLS custom nodes, so right after the streamlining transformations and before the nodes are converted into HLS layers.
Simulation using C++
====================
--
GitLab