From 62b7513165e76917d7c13fad1c4de36a67a938c3 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 29 Apr 2020 13:35:40 +0100
Subject: [PATCH] [PYNQ, IPStitch] introduce fclk as explicit parameter
set to a constant in the code for now, will move to attribute
---
src/finn/transformation/fpgadataflow/codegen_ipstitch.py | 2 ++
src/finn/transformation/fpgadataflow/make_pynq_proj.py | 3 +++
src/finn/transformation/fpgadataflow/templates.py | 5 +++++
3 files changed, 10 insertions(+)
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
index ace8dfaf6..388e1b364 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
+++ b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
@@ -147,6 +147,8 @@ class CodeGen_ipstitch(Transformation):
tcl.append('create_bd_design "%s"' % block_name)
tcl.extend(create_cmds)
tcl.extend(connect_cmds)
+ fclk_hz = 150 * 1000000
+ tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
tcl.append("regenerate_bd_layout")
tcl.append("validate_bd_design")
tcl.append("save_bd_design")
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 1e479f24d..981057b26 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -110,6 +110,8 @@ class MakePYNQProject(Transformation):
nrst_name = "ap_rst_n_0"
axi_lite_if_name = "s_axi_control_0"
vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
+ # TODO get from Transformation arg or metadata_prop
+ fclk_mhz = 150.0
# create a temporary folder for the project
vivado_pynq_proj_dir = make_build_dir(prefix="vivado_pynq_proj_")
@@ -132,6 +134,7 @@ class MakePYNQProject(Transformation):
nrst_name,
axi_lite_if_name,
vivado_ip_cache,
+ fclk_mhz,
)
with open(vivado_pynq_proj_dir + "/ip_config.tcl", "w") as f:
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index 6ff4a4f0b..033706172 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -26,6 +26,8 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# flake8: noqa
+
# template for the PYNQ shell integration configuration tcl script
ip_config_tcl_template = """
variable config_ip_repo
@@ -40,6 +42,7 @@ variable config_ip_project_dir
variable config_output_products_dir
variable config_remote_cache
variable config_util_report_filename
+variable config_ip_fclk
# for arguments involving paths below: use absolute paths or relative to the
# platform/overlay/bitstream folder
@@ -73,6 +76,8 @@ set config_ip_use_axilite 1
set config_ip_axilite_name %s
# Vivado OOC IP cache
set config_remote_cache "%s"
+# clock frequency
+set config_ip_fclk %f
"""
call_pynqshell_makefile_template = """
--
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