From 61a293a3871253cc1859a8f2facd36a7c7a016f7 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sat, 13 Nov 2021 01:12:08 +0100
Subject: [PATCH] [SWG] no parallel window output with bram/uram ram_style from
1D SWG
---
src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
index 89b3fd45e..6347c9e9e 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
@@ -217,12 +217,13 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
dilation = self.get_nodeattr("Dilation")
stride_h, stride_w = stride
dilation_h, dilation_w = dilation
+ ram_style = self.get_nodeattr("ram_style")
if self.get_nodeattr("SIMD") == self.get_nodeattr("IFMChannels"):
if self.get_nodeattr("depthwise") == 0:
if stride_h == 1 and stride_w == 1:
if dilation_h == 1 and dilation_w == 1:
- return True
+ return ram_style in ["auto", "distributed"]
return False
--
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