From 619feae58ebeaf3486a1bb137c365c06226d464d Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 8 May 2020 00:18:00 +0100
Subject: [PATCH] [Refactor] Codegen_ipstitch renamed to CreateStitchedIP
---
docs/finn/source_code/finn.transformation.fpgadataflow.rst | 5 ++---
notebooks/end2end_example/cnv_end2end_example.ipynb | 4 ++--
notebooks/end2end_example/tfc_end2end_example.ipynb | 6 +++---
.../{codegen_ipstitch.py => create_stitched_ip.py} | 2 +-
src/finn/transformation/fpgadataflow/make_pynq_proj.py | 6 +++---
tests/end2end/test_end2end_cnv_w1a1.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a1_throughput_test.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a2.py | 4 ++--
tests/end2end/test_end2end_tfc_w2a2.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_fifo.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_ip_stitch.py | 4 ++--
11 files changed, 23 insertions(+), 24 deletions(-)
rename src/finn/transformation/fpgadataflow/{codegen_ipstitch.py => create_stitched_ip.py} (99%)
diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
index e80ddbdd0..c4afa056f 100644
--- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
@@ -1,5 +1,5 @@
*****************************
-Transformation - fpgadataflow
+Transformation - fpgadataflow
*****************************
Transformations (fpgadataflow)
@@ -24,7 +24,7 @@ finn.transformation.fpgadataflow.codegen\_ipgen
finn.transformation.fpgadataflow.codegen\_ipstitch
--------------------------------------------------
-.. automodule:: finn.transformation.fpgadataflow.codegen_ipstitch
+.. automodule:: finn.transformation.fpgadataflow.create_stitched_ip
:members:
:undoc-members:
:show-inheritance:
@@ -140,4 +140,3 @@ finn.transformation.fpgadataflow.templates
:members:
:undoc-members:
:show-inheritance:
-
diff --git a/notebooks/end2end_example/cnv_end2end_example.ipynb b/notebooks/end2end_example/cnv_end2end_example.ipynb
index eda58eebf..d465e6afb 100644
--- a/notebooks/end2end_example/cnv_end2end_example.ipynb
+++ b/notebooks/end2end_example/cnv_end2end_example.ipynb
@@ -492,11 +492,11 @@
"from finn.transformation.fpgadataflow.replace_verilog_relpaths import (\n",
" ReplaceVerilogRelPaths,\n",
")\n",
- "from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch\n",
+ "from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP\n",
"\n",
"model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_ipgen.onnx\")\n",
"model = model.transform(ReplaceVerilogRelPaths())\n",
- "model = model.transform(CodeGen_ipstitch(test_fpga_part))\n",
+ "model = model.transform(CreateStitchedIP(test_fpga_part))\n",
"model.save(build_dir + \"/end2end_cnv_w1a1_ipstitch.onnx\")"
]
},
diff --git a/notebooks/end2end_example/tfc_end2end_example.ipynb b/notebooks/end2end_example/tfc_end2end_example.ipynb
index a0e905c83..b149bd0f3 100644
--- a/notebooks/end2end_example/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_example.ipynb
@@ -1160,7 +1160,7 @@
"source": [
"### IP Stitching <a id='ip_stitching'></a>\n",
"\n",
- "We now have IP blocks for each of our layers, and will stitch them together into a larger IP that implements the whole network using the `CodeGen_ipstitch` transformation. Bear in mind that this transformation can only be applied on a graph that only contains HLS nodes that already have been through the `HLSSynth_IPGen` transformation, which is the last step we performed. Prior to calling IP stitching, we'll also use the `ReplaceVerilogRelPaths` transformation to convert any relative `$readmemh` paths in the generated IP blocks to absolute ones, which prevents errors later on. **This step invokes Vivado and may take a few minutes to run.**"
+ "We now have IP blocks for each of our layers, and will stitch them together into a larger IP that implements the whole network using the `CreateStitchedIP` transformation. Bear in mind that this transformation can only be applied on a graph that only contains HLS nodes that already have been through the `HLSSynth_IPGen` transformation, which is the last step we performed. Prior to calling IP stitching, we'll also use the `ReplaceVerilogRelPaths` transformation to convert any relative `$readmemh` paths in the generated IP blocks to absolute ones, which prevents errors later on. **This step invokes Vivado and may take a few minutes to run.**"
]
},
{
@@ -1169,11 +1169,11 @@
"metadata": {},
"outputs": [],
"source": [
- "from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch\n",
+ "from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP\n",
"from finn.transformation.fpgadataflow.replace_verilog_relpaths import ReplaceVerilogRelPaths\n",
"model = ModelWrapper(build_dir+\"/tfc_w1_a1_ipgen.onnx\")\n",
"model = model.transform(ReplaceVerilogRelPaths())\n",
- "model = model.transform(CodeGen_ipstitch(fpga_part))"
+ "model = model.transform(CreateStitchedIP(fpga_part))"
]
},
{
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
similarity index 99%
rename from src/finn/transformation/fpgadataflow/codegen_ipstitch.py
rename to src/finn/transformation/fpgadataflow/create_stitched_ip.py
index bc1fce836..848c2068d 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -34,7 +34,7 @@ from finn.util.basic import get_by_name, make_build_dir
from finn.custom_op.registry import getCustomOp
-class CodeGen_ipstitch(Transformation):
+class CreateStitchedIP(Transformation):
"""Create a Vivado IP Block Design project from all the generated IPs of a
graph. All nodes in the graph must have the fpgadataflow backend attribute,
and the CodeGen_ipgen transformation must have been previously run on
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 9fe5781ec..429b74bb5 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -40,7 +40,7 @@ class MakePYNQProject(Transformation):
"""Create a Vivado PYNQ overlay project (including the shell infrastructure)
from the already-stitched IP block for this graph.
All nodes in the graph must have the fpgadataflow backend attribute,
- and the CodeGen_ipstitch transformation must have been previously run on
+ and the CreateStitchedIP transformation must have been previously run on
the graph.
Outcome if successful: sets the vivado_pynq_proj attribute in the ONNX
@@ -59,12 +59,12 @@ class MakePYNQProject(Transformation):
ipstitch_path = model.get_metadata_prop("vivado_stitch_proj")
if ipstitch_path is None or (not os.path.isdir(ipstitch_path)):
raise Exception(
- "No stitched IPI design found, apply CodeGen_ipstitch first."
+ "No stitched IPI design found, apply CreateStitchedIP first."
)
vivado_stitch_vlnv = model.get_metadata_prop("vivado_stitch_vlnv")
if vivado_stitch_vlnv is None:
raise Exception(
- "No vlnv for stitched IP found, apply CodeGen_ipstitch first."
+ "No vlnv for stitched IP found, apply CreateStitchedIP first."
)
# collect list of all IP dirs
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
index 1725eb391..f6b4d8990 100644
--- a/tests/end2end/test_end2end_cnv_w1a1.py
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -60,7 +60,7 @@ from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
ReplaceVerilogRelPaths,
)
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
@@ -178,7 +178,7 @@ def test_end2end_cnv_w1a1_gen_hls_ip():
def test_end2end_cnv_w1a1_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
model.save(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index ea7ce9df8..1cce1c55a 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -47,7 +47,7 @@ from finn.custom_op.registry import getCustomOp
from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
from finn.transformation.fold_constants import FoldConstants
from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
from finn.transformation.fpgadataflow.create_dataflow_partition import (
@@ -164,7 +164,7 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
def test_end2end_tfc_w1a1_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index 6d0349057..a6516b8ea 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -44,7 +44,7 @@ from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
from finn.transformation.fold_constants import FoldConstants
from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
from finn.transformation.fpgadataflow.create_dataflow_partition import (
@@ -156,7 +156,7 @@ def test_end2end_tfc_w1a2_gen_hls_ip():
def test_end2end_tfc_w1a2_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
index f1ded9ab0..c33525428 100644
--- a/tests/end2end/test_end2end_tfc_w2a2.py
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -44,7 +44,7 @@ from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
from finn.transformation.fold_constants import FoldConstants
from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
from finn.transformation.fpgadataflow.create_dataflow_partition import (
@@ -156,7 +156,7 @@ def test_end2end_tfc_w2a2_gen_hls_ip():
def test_end2end_tfc_w2a2_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
model.save(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
index 8ab480992..139ce3848 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fifo.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -6,7 +6,7 @@ from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
@@ -98,7 +98,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
assert y.shape == tuple(Shape), """The output shape is incorrect."""
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
model = model.transform(MakePYNQProject(test_pynq_board))
model = model.transform(SynthPYNQProject())
model = model.transform(MakePYNQDriver())
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index af0c7b075..3d8e17d85 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -38,7 +38,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
-from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
@@ -220,7 +220,7 @@ def test_fpgadataflow_ipstitch_do_stitch():
ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx"
)
model = model.transform(rvp.ReplaceVerilogRelPaths())
- model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part))
vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
assert vivado_stitch_proj_dir is not None
assert os.path.isdir(vivado_stitch_proj_dir)
--
GitLab