From 60ae8b3a3fa485e0aaee0863d64e1e032687cc0e Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Wed, 29 Apr 2020 15:30:49 +0100
Subject: [PATCH] [HLSCustomOp] Change default depth for FIFO related node
attributes to 2
---
src/finn/custom_op/fpgadataflow/__init__.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index 3091245b8..38c2ed663 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -83,8 +83,8 @@ class HLSCustomOp(CustomOp):
"res_synth": ("s", False, ""),
"rtlsim_so": ("s", False, ""),
# input and output FIFO depths
- "inFIFODepth": ("i", False, 0),
- "outFIFODepth": ("i", False, 0),
+ "inFIFODepth": ("i", False, 2),
+ "outFIFODepth": ("i", False, 2),
}
def get_verilog_top_module_name(self):
--
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