From 5e940096e7299ac18675e8cb9e744250c8c4816f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= <thomas.preusser@xilinx.com>
Date: Tue, 16 May 2023 08:45:28 +0100
Subject: [PATCH] Linting.
---
.../fpgadataflow/create_stitched_ip.py | 85 ++++++++++---------
1 file changed, 45 insertions(+), 40 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 03212a9f1..ef1afb95c 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -386,7 +386,7 @@ class CreateStitchedIP(Transformation):
% (prjname, vivado_stitch_proj_dir, self.fpgapart)
)
# no warnings on long module names
- tcl.append("set_msg_config -id {[BD 41-1753]} -suppress");
+ tcl.append("set_msg_config -id {[BD 41-1753]} -suppress")
# add all the generated IP dirs to ip_repo_paths
ip_dirs_str = " ".join(ip_dirs)
tcl.append("set_property ip_repo_paths [%s] [current_project]" % ip_dirs_str)
@@ -399,7 +399,9 @@ class CreateStitchedIP(Transformation):
fclk_mhz = 1 / (self.clk_ns * 0.001)
fclk_hz = fclk_mhz * 1000000
model.set_metadata_prop("clk_ns", str(self.clk_ns))
- tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz))
+ tcl.append(
+ "set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)
+ )
tcl.append("validate_bd_design")
tcl.append("save_bd_design")
# create wrapper hdl (for rtlsim later on)
@@ -452,7 +454,7 @@ class CreateStitchedIP(Transformation):
% (vivado_stitch_proj_dir, block_vendor, block_library, block_name)
)
# Allow user to customize clock in deployment of stitched IP
- tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]");
+ tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]")
# in some cases, the IP packager seems to infer an aperture of 64K or 4G,
# preventing address assignment of the DDR_LOW and/or DDR_HIGH segments
# the following is a hotfix to remove this aperture during IODMA packaging
@@ -550,7 +552,8 @@ class CreateStitchedIP(Transformation):
#####
# Core Cleanup Operations
- tcl.append("""
+ tcl.append(
+ """
set core [ipx::current_core]
# Add rudimentary driver
@@ -567,25 +570,26 @@ foreach xci [ipx::get_files -of $impl_files {*.xci}] {
# Construct a single flat memory map for each AXI-lite interface port
foreach port [get_bd_intf_ports -filter {CONFIG.PROTOCOL==AXI4LITE}] {
- set pin $port
- set awidth ""
- while { $awidth == "" } {
- set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]]
- set kill [lsearch $pins $pin]
- if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] }
- if { [llength $pins] != 1 } { break }
- set pin [lindex $pins 0]
- set awidth [get_property CONFIG.ADDR_WIDTH $pin]
- }
- if { $awidth == "" } {
- puts "CRITICAL WARNING: Unable to construct address map for $port."
- } {
- set range [expr 2**$awidth]
- puts "INFO: Building address map for $port 0+:$range"
- set name [get_property NAME $port]
- set_property range $range [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]]
- set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core]
- }
+ set pin $port
+ set awidth ""
+ while { $awidth == "" } {
+ set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]]
+ set kill [lsearch $pins $pin]
+ if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] }
+ if { [llength $pins] != 1 } { break }
+ set pin [lindex $pins 0]
+ set awidth [get_property CONFIG.ADDR_WIDTH $pin]
+ }
+ if { $awidth == "" } {
+ puts "CRITICAL WARNING: Unable to construct address map for $port."
+ } {
+ set range [expr 2**$awidth]
+ puts "INFO: Building address map for $port: 0+:$range"
+ set name [get_property NAME $port]
+ set addr_block [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]]
+ set_property range $range $addr_block
+ set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core]
+ }
}
# Finalize and Save
@@ -599,27 +603,28 @@ set ofile [open ip/component.xml w]
set buf [list]
set kill 0
while { [eof $ifile] != 1 } {
- gets $ifile line
- if { [string match {*<spirit:fileSet>*} $line] == 1 } {
- foreach l $buf { puts $ofile $l }
- set buf [list $line]
- } elseif { [llength $buf] > 0 } {
- lappend buf $line
+ gets $ifile line
+ if { [string match {*<spirit:fileSet>*} $line] == 1 } {
+ foreach l $buf { puts $ofile $l }
+ set buf [list $line]
+ } elseif { [llength $buf] > 0 } {
+ lappend buf $line
- if { [string match {*</spirit:fileSet>*} $line] == 1 } {
- if { $kill == 0 } { foreach l $buf { puts $ofile $l } }
- set buf [list]
- set kill 0
- } elseif { [string match {*<xilinx:subCoreRef>*} $line] == 1 } {
- set kill 1
- }
- } else {
- puts $ofile $line
- }
+ if { [string match {*</spirit:fileSet>*} $line] == 1 } {
+ if { $kill == 0 } { foreach l $buf { puts $ofile $l } }
+ set buf [list]
+ set kill 0
+ } elseif { [string match {*<xilinx:subCoreRef>*} $line] == 1 } {
+ set kill 1
+ }
+ } else {
+ puts $ofile $line
+ }
}
close $ifile
close $ofile
-""");
+"""
+ )
# export list of used Verilog files (for rtlsim later on)
tcl.append(
--
GitLab