From 5e6308340f2b6afb80f1c212bce000a5aa0f94a9 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 8 May 2020 00:40:46 +0100
Subject: [PATCH] [Refactor] rename HLSSynth_IPGen to HLSSynthIP
---
.../source_code/finn.transformation.fpgadataflow.rst | 2 +-
notebooks/advanced/1_custom_transformation_pass.ipynb | 2 +-
notebooks/end2end_example/cnv_end2end_example.ipynb | 4 ++--
notebooks/end2end_example/tfc_end2end_example.ipynb | 10 +++++-----
.../analysis/fpgadataflow/hls_synth_res_estimation.py | 4 ++--
src/finn/custom_op/fpgadataflow/__init__.py | 2 +-
.../transformation/fpgadataflow/annotate_resources.py | 2 +-
.../fpgadataflow/{hlssynth_ipgen.py => hlssynth_ip.py} | 4 ++--
src/finn/transformation/fpgadataflow/prepare_ip.py | 2 +-
src/finn/transformation/fpgadataflow/prepare_rtlsim.py | 2 +-
tests/end2end/test_end2end_cnv_w1a1.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a1_throughput_test.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a2.py | 4 ++--
tests/end2end/test_end2end_tfc_w2a2.py | 4 ++--
.../test_fpgadataflow_convinputgenerator.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_dwc.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_fclayer.py | 6 +++---
tests/fpgadataflow/test_fpgadataflow_fifo.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_ip_stitch.py | 4 ++--
.../fpgadataflow/test_layer_streaming_maxpool_batch.py | 4 ++--
20 files changed, 38 insertions(+), 38 deletions(-)
rename src/finn/transformation/fpgadataflow/{hlssynth_ipgen.py => hlssynth_ip.py} (96%)
diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
index e57314ea1..968587535 100644
--- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
@@ -64,7 +64,7 @@ finn.transformation.fpgadataflow.create\_dataflow\_partition
finn.transformation.fpgadataflow.hlssynth\_ipgen
------------------------------------------------
-.. automodule:: finn.transformation.fpgadataflow.hlssynth_ipgen
+.. automodule:: finn.transformation.fpgadataflow.hlssynth_ip
:members:
:undoc-members:
:show-inheritance:
diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb
index 3f8de434d..7ff850e7b 100644
--- a/notebooks/advanced/1_custom_transformation_pass.ipynb
+++ b/notebooks/advanced/1_custom_transformation_pass.ipynb
@@ -442,7 +442,7 @@
"source": [
"At the moment FINN supports parallelization for the following transformations:\n",
"* `CompileCppSim` (Compilation of the generated c++ code for each node)\n",
- "* `HLSSynth_IPGen` (Synthesis and ip block generation of the hls code for each node)\n",
+ "* `HLSSynthIP` (Synthesis and ip block generation of the hls code for each node)\n",
"* `PrepareRTLSim` (Creation of the files to emulate a node using PyVerilator)"
]
}
diff --git a/notebooks/end2end_example/cnv_end2end_example.ipynb b/notebooks/end2end_example/cnv_end2end_example.ipynb
index 2c1e269a5..adb34f6d1 100644
--- a/notebooks/end2end_example/cnv_end2end_example.ipynb
+++ b/notebooks/end2end_example/cnv_end2end_example.ipynb
@@ -463,7 +463,7 @@
"outputs": [],
"source": [
"from finn.transformation.fpgadataflow.prepare_ip import PrepareIP\n",
- "from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen\n",
+ "from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP\n",
"from finn.util.basic import pynq_part_map\n",
"\n",
"test_pynq_board = \"Pynq-Z1\"\n",
@@ -472,7 +472,7 @@
"\n",
"model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_folded.onnx\")\n",
"model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))\n",
- "model = model.transform(HLSSynth_IPGen())\n",
+ "model = model.transform(HLSSynthIP())\n",
"model.save(build_dir + \"/end2end_cnv_w1a1_ipgen.onnx\")"
]
},
diff --git a/notebooks/end2end_example/tfc_end2end_example.ipynb b/notebooks/end2end_example/tfc_end2end_example.ipynb
index 83c7ec4a6..bcb54adf2 100644
--- a/notebooks/end2end_example/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_example.ipynb
@@ -949,7 +949,7 @@
"source": [
"Two transformations are required to generate HLS IP blocks for each layer: \n",
"* `PrepareIP` which generates the HLS C++ code for the node and a tcl-script which starts the HLS synthesis and exports the design as IP. \n",
- "* `HLSSynth_IPGen` which passes the tcl-script to Vivado HLS and thus performs the actual IP generation. \n",
+ "* `HLSSynthIP` which passes the tcl-script to Vivado HLS and thus performs the actual IP generation. \n",
"\n",
"We start off by giving unique node names using the basic transformation `GiveUniqueNodeNames`, and then proceed with the HLS C++ code generation with `PrepareIP`."
]
@@ -973,7 +973,7 @@
"source": [
"### Synthesizing HLS to IP Blocks <a id='hls_synth'></a>\n",
"\n",
- "Now that we have generated the HLS code for each layer, we can call the `HLSSynth_IPGen` transformation to convert the generated HLS into Vivado IP blocks. **As this involves calling HLS synthesis, this transformation will run for some time (several minutes).**"
+ "Now that we have generated the HLS code for each layer, we can call the `HLSSynthIP` transformation to convert the generated HLS into Vivado IP blocks. **As this involves calling HLS synthesis, this transformation will run for some time (several minutes).**"
]
},
{
@@ -982,9 +982,9 @@
"metadata": {},
"outputs": [],
"source": [
- "from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen\n",
+ "from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP\n",
"\n",
- "model = model.transform(HLSSynth_IPGen())\n",
+ "model = model.transform(HLSSynthIP())\n",
"model.save(build_dir+\"/tfc_w1_a1_ipgen.onnx\")"
]
},
@@ -1160,7 +1160,7 @@
"source": [
"### IP Stitching <a id='ip_stitching'></a>\n",
"\n",
- "We now have IP blocks for each of our layers, and will stitch them together into a larger IP that implements the whole network using the `CreateStitchedIP` transformation. Bear in mind that this transformation can only be applied on a graph that only contains HLS nodes that already have been through the `HLSSynth_IPGen` transformation, which is the last step we performed. Prior to calling IP stitching, we'll also use the `ReplaceVerilogRelPaths` transformation to convert any relative `$readmemh` paths in the generated IP blocks to absolute ones, which prevents errors later on. **This step invokes Vivado and may take a few minutes to run.**"
+ "We now have IP blocks for each of our layers, and will stitch them together into a larger IP that implements the whole network using the `CreateStitchedIP` transformation. Bear in mind that this transformation can only be applied on a graph that only contains HLS nodes that already have been through the `HLSSynthIP` transformation, which is the last step we performed. Prior to calling IP stitching, we'll also use the `ReplaceVerilogRelPaths` transformation to convert any relative `$readmemh` paths in the generated IP blocks to absolute ones, which prevents errors later on. **This step invokes Vivado and may take a few minutes to run.**"
]
},
{
diff --git a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
index 968e09263..ad30282d9 100644
--- a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
+++ b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
@@ -55,7 +55,7 @@ def hls_synth_res_estimation(model):
warnings.warn(
"""Could not find report files, values will be set to zero
for this node. Please run "PrepareIP" transformation and
- "HLSSynth_IPGen" first to generate the report files"""
+ "HLSSynthIP" first to generate the report files"""
)
else:
xmlfile = "{}/project_{}/sol1/syn/report/{}_csynth.xml".format(
@@ -72,6 +72,6 @@ def hls_synth_res_estimation(model):
warnings.warn(
"""Could not find report files, values will be set to zero
for this node. Please run "PrepareIP" transformation and
- "HLSSynth_IPGen" first to generate the report files"""
+ "HLSSynthIP" first to generate the report files"""
)
return res_dict
diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index 8e61b362d..65ad469ca 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -121,7 +121,7 @@ class HLSCustomOp(CustomOp):
assert (
code_gen_dir != ""
), """Node attribute "code_gen_dir_ipgen" is
- not set. Please run HLSSynth_IPGen first."""
+ not set. Please run HLSSynthIP first."""
verilog_file = self.get_verilog_top_filename()
assert os.path.isfile(verilog_file), "Cannot find top-level Verilog file."
# build the Verilator emu library
diff --git a/src/finn/transformation/fpgadataflow/annotate_resources.py b/src/finn/transformation/fpgadataflow/annotate_resources.py
index d192372a7..207075b00 100644
--- a/src/finn/transformation/fpgadataflow/annotate_resources.py
+++ b/src/finn/transformation/fpgadataflow/annotate_resources.py
@@ -41,7 +41,7 @@ class AnnotateResources(Transformation):
* 'hls' -- use results from the HLS synthesis report
No annotations can be provided unless the relevant transformation for the
- chosen mode (e.g. HLSSynth_IPGen for hls) was previously run.
+ chosen mode (e.g. HLSSynthIP for hls) was previously run.
"""
def __init__(self, mode):
diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py b/src/finn/transformation/fpgadataflow/hlssynth_ip.py
similarity index 96%
rename from src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
rename to src/finn/transformation/fpgadataflow/hlssynth_ip.py
index f895b81c2..6d7c40256 100644
--- a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
+++ b/src/finn/transformation/fpgadataflow/hlssynth_ip.py
@@ -31,7 +31,7 @@ from finn.util.fpgadataflow import is_fpgadataflow_node
from finn.transformation import NodeLocalTransformation
-class HLSSynth_IPGen(NodeLocalTransformation):
+class HLSSynthIP(NodeLocalTransformation):
"""For each node: generate IP block from code in folder
that is referenced in node attribute "code_gen_dir_ipgen"
and save path of generated project in node attribute "ipgen_path".
@@ -65,7 +65,7 @@ class HLSSynth_IPGen(NodeLocalTransformation):
assert (
inst.get_nodeattr("ipgen_path") != ""
), """Transformation
- HLSSynth_IPGen was not successful. Node attribute "ipgen_path"
+ HLSSynthIP was not successful. Node attribute "ipgen_path"
is empty."""
except KeyError:
# exception if op_type is not supported
diff --git a/src/finn/transformation/fpgadataflow/prepare_ip.py b/src/finn/transformation/fpgadataflow/prepare_ip.py
index 1e2062e3b..001827735 100644
--- a/src/finn/transformation/fpgadataflow/prepare_ip.py
+++ b/src/finn/transformation/fpgadataflow/prepare_ip.py
@@ -69,7 +69,7 @@ class PrepareIP(Transformation):
Outcome if succesful: Node attribute "code_gen_dir_ipgen" contains path to folder
that contains generated C++ code that can be used to generate a Vivado IP block.
- The subsequent transformation is HLSSynth_IPGen"""
+ The subsequent transformation is HLSSynthIP"""
def __init__(self, fpgapart, clk):
super().__init__()
diff --git a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py
index baac3e7bd..5f0b89e85 100644
--- a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py
+++ b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py
@@ -38,7 +38,7 @@ except ModuleNotFoundError:
class PrepareRTLSim(NodeLocalTransformation):
- """For a graph with generated RTL sources (after HLSSynth_IPGen), create a
+ """For a graph with generated RTL sources (after HLSSynthIP), create a
Verilator emulation library for each node to prepare for rtlsim
execution and set the rtlsim_so property to the path to the generated
emulation library.
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
index c8c8bc311..94358ae48 100644
--- a/tests/end2end/test_end2end_cnv_w1a1.py
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -56,7 +56,7 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import (
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
ReplaceVerilogRelPaths,
)
@@ -170,7 +170,7 @@ def test_end2end_cnv_w1a1_fold_and_tlastmarker():
def test_end2end_cnv_w1a1_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_folded.onnx")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index e413b7532..80bfb0ee0 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -53,7 +53,7 @@ from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
@@ -156,7 +156,7 @@ def test_end2end_tfc_w1a1_fold_and_tlastmarker():
def test_end2end_tfc_w1a1_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_folded.onnx")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index ec4d86295..996d5dbcc 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -50,7 +50,7 @@ from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
@@ -148,7 +148,7 @@ def test_end2end_tfc_w1a2_fold_and_tlastmarker():
def test_end2end_tfc_w1a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_folded.onnx")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
index 7d0f0287e..fa0a3db2d 100644
--- a/tests/end2end/test_end2end_tfc_w2a2.py
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -50,7 +50,7 @@ from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
@@ -148,7 +148,7 @@ def test_end2end_tfc_w2a2_fold_and_tlastmarker():
def test_end2end_tfc_w2a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_folded.onnx")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
index 46cc78e3d..067bc228c 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
@@ -36,7 +36,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.general import GiveUniqueNodeNames
@@ -153,7 +153,7 @@ def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, exec_mode,
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
else:
raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow")
diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py
index 0a35b7832..a230fb420 100644
--- a/tests/fpgadataflow/test_fpgadataflow_dwc.py
+++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py
@@ -5,7 +5,7 @@ from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.general import GiveUniqueNodeNames
@@ -66,7 +66,7 @@ def test_fpgadataflow_dwc_rtlsim(Shape, INWidth, OUTWidth, finn_dtype):
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
y = oxe.execute_onnx(model, input_dict)["outp"]
diff --git a/tests/fpgadataflow/test_fpgadataflow_fclayer.py b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
index 127053828..f0484895d 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fclayer.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
@@ -41,7 +41,7 @@ from finn.custom_op.multithreshold import multithreshold
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.general import GiveUniqueNodeNames
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
@@ -298,7 +298,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(ReplaceVerilogRelPaths())
model = model.transform(PrepareRTLSim())
y_produced = oxe.execute_onnx(model, input_dict)["outp"]
@@ -390,7 +390,7 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode(
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(ReplaceVerilogRelPaths())
model = model.transform(PrepareRTLSim())
y_produced = oxe.execute_onnx(model, input_dict)["outp"]
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
index 14efa0683..fe27d7d42 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fifo.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -8,7 +8,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.general import GiveUniqueNodeNames
@@ -88,7 +88,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
y = oxe.execute_onnx(model, input_dict)["outp"]
assert (
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index 47352eeb9..f26ba428b 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -42,7 +42,7 @@ from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
@@ -209,7 +209,7 @@ def test_fpgadataflow_ipstitch_gen_model(): # exec_mode):
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP(test_fpga_part, 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
assert model.graph.node[0].op_type == "StreamingFCLayer_Batch"
assert model.graph.node[-1].op_type == "TLastMarker"
model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx")
diff --git a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
index a2a522b12..6d4b80671 100644
--- a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
+++ b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
@@ -36,7 +36,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
-from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.general import GiveUniqueNodeNames
@@ -144,7 +144,7 @@ def test_fpgadataflow_streamingmaxpool(idt, k, ifm_dim, ifm_ch, exec_mode):
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
+ model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
else:
raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow")
--
GitLab