From 584f0fb5d07e2719d03bbfbbc8f34bb6d35a12ce Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Mon, 26 Sep 2022 16:43:06 +0100
Subject: [PATCH] [customOp] Temp. reverse changes to checksum axilite
interface name
---
src/finn/custom_op/fpgadataflow/checksum.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py
index 7510e1013..bde285eb0 100644
--- a/src/finn/custom_op/fpgadataflow/checksum.py
+++ b/src/finn/custom_op/fpgadataflow/checksum.py
@@ -329,5 +329,5 @@ class CheckSum(HLSCustomOp):
def get_verilog_top_module_intf_names(self):
intf_names = super().get_verilog_top_module_intf_names()
# expose axilite interface
- intf_names["axilite"] = ["s_axilite_checksum"]
+ intf_names["axilite"] = ["s_axi_checksum"]
return intf_names
--
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