diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml
index 63a8540a76a100201c67d7a1dcbaec15f10e1c0e..2705f619089007229af04d7ecdd5d95b4e67b957 100644
--- a/finn-rtllib/memstream/component.xml
+++ b/finn-rtllib/memstream/component.xml
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>user</spirit:library>
+ <spirit:vendor>amd.com</spirit:vendor>
+ <spirit:library>FINN</spirit:library>
<spirit:name>memstream</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -37,201 +37,6 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_1" xilinx:dependency="$NSTREAMS>=2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_2</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_2" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_3</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_3" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_4</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_4" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_5</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_5" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>s_axilite</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
@@ -393,16 +198,9 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axilite" xilinx:dependency="$CONFIG_EN = 1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
@@ -412,19 +210,23 @@
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.ASSOCIATED_BUSIF">m_axis_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
@@ -434,18 +236,22 @@
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5:s_axilite</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">m_axis_0:s_axilite</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -453,11 +259,13 @@
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>interface_aximm</spirit:name>
+ <spirit:displayName>interface_aximm</spirit:displayName>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
- <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
- <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="4096" spirit:rangeType="long">65536</spirit:range>
- <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+ <spirit:displayName>reg0</spirit:displayName>
+ <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
+ <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1) - 0 + 1)" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
+ <spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
@@ -468,31 +276,15 @@
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
- <spirit:language>Verilog</spirit:language>
- <spirit:modelName>memstream</spirit:modelName>
+ <spirit:language>SystemVerilog</spirit:language>
+ <spirit:modelName>memstream_axi_wrapper</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>1fc5a310</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:view>
- <spirit:view>
- <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
- <spirit:displayName>Simulation</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
- <spirit:language>Verilog</spirit:language>
- <spirit:modelName>memstream</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>viewChecksum</spirit:name>
- <spirit:value>d02d9990</spirit:value>
+ <spirit:value>4d23c8e5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -506,48 +298,32 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>f960907f</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:view>
- <spirit:view>
- <spirit:name>xilinx_utilityxitfiles</spirit:name>
- <spirit:displayName>Utility XIT/TTCL</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>viewChecksum</spirit:name>
- <spirit:value>d2aad2c5</spirit:value>
+ <spirit:value>91d40e29</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -560,7 +336,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -573,7 +348,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -582,18 +356,17 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>awaddr</spirit:name>
+ <spirit:name>awprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
+ <spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -602,18 +375,17 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>awprot</spirit:name>
+ <spirit:name>awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">10</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -629,7 +401,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -642,7 +413,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -662,7 +432,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -682,7 +451,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -698,7 +466,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -714,7 +481,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -731,7 +497,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -744,7 +509,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -757,7 +521,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -766,18 +529,17 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>araddr</spirit:name>
+ <spirit:name>arprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
+ <spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -786,18 +548,17 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>arprot</spirit:name>
+ <spirit:name>araddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">10</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -813,7 +574,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -829,7 +589,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -846,7 +605,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -863,33 +621,9 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_0_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_0_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_0_tready</spirit:name>
@@ -899,7 +633,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -915,7 +648,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -925,359 +657,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM0_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_1_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM1_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_2_afull" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM2_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_3_afull" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM3_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_4_afull" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM4_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_5_afull" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM5_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1285,129 +671,29 @@
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
- <spirit:name>CONFIG_EN</spirit:name>
- <spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONFIG_EN">true</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>NSTREAMS</spirit:name>
- <spirit:displayName>Nstreams</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NSTREAMS">6</spirit:value>
+ <spirit:name>DEPTH</spirit:name>
+ <spirit:displayName>Depth</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEPTH">512</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
- <spirit:name>MEM_DEPTH</spirit:name>
- <spirit:displayName>Mem Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_DEPTH">13824</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>MEM_WIDTH</spirit:name>
- <spirit:displayName>Mem Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_WIDTH">32</spirit:value>
+ <spirit:name>WIDTH</spirit:name>
+ <spirit:displayName>Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
- <spirit:name>MEM_INIT</spirit:name>
- <spirit:displayName>Mem Init</spirit:displayName>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_INIT">./</spirit:value>
+ <spirit:name>INIT_FILE</spirit:name>
+ <spirit:displayName>Init File</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INIT_FILE"/>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>RAM_STYLE</spirit:name>
<spirit:displayName>Ram Style</spirit:displayName>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RAM_STYLE">auto</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_WIDTH</spirit:name>
- <spirit:displayName>Strm0 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_WIDTH</spirit:name>
- <spirit:displayName>Strm1 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_WIDTH</spirit:name>
- <spirit:displayName>Strm2 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_WIDTH</spirit:name>
- <spirit:displayName>Strm3 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_WIDTH</spirit:name>
- <spirit:displayName>Strm4 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_WIDTH</spirit:name>
- <spirit:displayName>Strm5 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_DEPTH</spirit:name>
- <spirit:displayName>Strm0 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_DEPTH</spirit:name>
- <spirit:displayName>Strm1 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_DEPTH</spirit:name>
- <spirit:displayName>Strm2 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_DEPTH</spirit:name>
- <spirit:displayName>Strm3 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_DEPTH</spirit:name>
- <spirit:displayName>Strm4 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_DEPTH</spirit:name>
- <spirit:displayName>Strm5 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_OFFSET</spirit:name>
- <spirit:displayName>Strm0 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_OFFSET">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_OFFSET</spirit:name>
- <spirit:displayName>Strm1 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_OFFSET">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_OFFSET</spirit:name>
- <spirit:displayName>Strm2 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_OFFSET">4608</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_OFFSET</spirit:name>
- <spirit:displayName>Strm3 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_OFFSET">6912</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_OFFSET</spirit:name>
- <spirit:displayName>Strm4 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_OFFSET">9216</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_OFFSET</spirit:name>
- <spirit:displayName>Strm5 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
- </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
<spirit:displayName>Axilite Addr Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_ADDR_WIDTH" spirit:dependency="(2 + spirit:ceil(spirit:log(2,(spirit:decode(id('MODELPARAM_VALUE.MEM_DEPTH')) * (1 << spirit:ceil(spirit:log(2,((spirit:decode(id('MODELPARAM_VALUE.MEM_WIDTH')) + 31) / 32))))))))">16</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.AXILITE_ADDR_WIDTH" spirit:dependency="(spirit:ceil(spirit:log(2,(spirit:decode(id('MODELPARAM_VALUE.DEPTH')) * (2 ** spirit:ceil(spirit:log(2,((spirit:decode(id('MODELPARAM_VALUE.WIDTH')) + 31) / 32))))))) + 2)">11</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
@@ -1417,13 +703,6 @@
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_e2bd1cd0</spirit:name>
- <spirit:enumeration>auto</spirit:enumeration>
- <spirit:enumeration>distributed</spirit:enumeration>
- <spirit:enumeration>block</spirit:enumeration>
- <spirit:enumeration>ultra</spirit:enumeration>
- </spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
@@ -1433,74 +712,17 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/memstream_singleblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream_axi.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/ramb18_sdp.v</spirit:name>
+ <spirit:name>hdl/memstream_axi_wrapper.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_9425c051</spirit:userFileType>
- </spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>hdl/memstream.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/axilite_if.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/memstream_singleblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_sdp.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ <spirit:userFileType>CHECKSUM_a3b36ea4</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -1508,200 +730,110 @@
<spirit:file>
<spirit:name>xgui/memstream_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_f960907f</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_91d40e29</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>gui/memstream_v1_0.gtcl</spirit:name>
- <spirit:userFileType>GTCL</spirit:userFileType>
- </spirit:file>
- </spirit:fileSet>
</spirit:fileSets>
- <spirit:description>memstream_v1_0</spirit:description>
+ <spirit:description>memstream</spirit:description>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>CONFIG_EN</spirit:name>
- <spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CONFIG_EN">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>NSTREAMS</spirit:name>
- <spirit:displayName>Nstreams</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NSTREAMS" spirit:minimum="1" spirit:maximum="6" spirit:rangeType="long">6</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>MEM_DEPTH</spirit:name>
- <spirit:displayName>Mem Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_DEPTH">13824</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>MEM_WIDTH</spirit:name>
- <spirit:displayName>Mem Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>MEM_INIT</spirit:name>
- <spirit:displayName>Mem Init</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_INIT">./</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RAM_STYLE</spirit:name>
- <spirit:displayName>Ram Style</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE" spirit:choiceRef="choice_list_e2bd1cd0">auto</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_WIDTH</spirit:name>
- <spirit:displayName>Strm0 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_WIDTH</spirit:name>
- <spirit:displayName>Strm1 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_WIDTH</spirit:name>
- <spirit:displayName>Strm2 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_WIDTH</spirit:name>
- <spirit:displayName>Strm3 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_WIDTH</spirit:name>
- <spirit:displayName>Strm4 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_WIDTH</spirit:name>
- <spirit:displayName>Strm5 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_DEPTH</spirit:name>
- <spirit:displayName>Strm0 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_DEPTH</spirit:name>
- <spirit:displayName>Strm1 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_DEPTH</spirit:name>
- <spirit:displayName>Strm2 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_DEPTH</spirit:name>
- <spirit:displayName>Strm3 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_DEPTH</spirit:name>
- <spirit:displayName>Strm4 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_DEPTH</spirit:name>
- <spirit:displayName>Strm5 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_OFFSET</spirit:name>
- <spirit:displayName>Strm0 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_OFFSET">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_OFFSET</spirit:name>
- <spirit:displayName>Strm1 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_OFFSET">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_OFFSET</spirit:name>
- <spirit:displayName>Strm2 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_OFFSET">4608</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_OFFSET</spirit:name>
- <spirit:displayName>Strm3 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_OFFSET">6912</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_OFFSET</spirit:name>
- <spirit:displayName>Strm4 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_OFFSET">9216</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_OFFSET</spirit:name>
- <spirit:displayName>Strm5 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
+ <spirit:name>DEPTH</spirit:name>
+ <spirit:displayName>Depth</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEPTH">512</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:presence>required</xilinx:presence>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
- <spirit:displayName>Axilite Addr Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXILITE_ADDR_WIDTH">16</spirit:value>
+ <spirit:name>WIDTH</spirit:name>
+ <spirit:displayName>Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.AXILITE_ADDR_WIDTH">false</xilinx:isEnabled>
+ <xilinx:presence>required</xilinx:presence>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INIT_FILE</spirit:name>
+ <spirit:displayName>Init File</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INIT_FILE"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RAM_STYLE</spirit:name>
+ <spirit:displayName>Ram Style</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE">auto</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_axi_wrapper_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
- <xilinx:family xilinx:lifeCycle="Beta">aartix7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">akintex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">artix7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">artix7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">azynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qzynqplus</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">versalprime</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtexupluse58g</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>memstream_v1_0</xilinx:displayName>
+ <xilinx:displayName>memstream</xilinx:displayName>
+ <xilinx:autoFamilySupportLevel>level_0</xilinx:autoFamilySupportLevel>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
- <xilinx:coreRevision>5</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2020-10-09T15:31:57Z</xilinx:coreCreationDateTime>
+ <xilinx:vendorDisplayName>AMD</xilinx:vendorDisplayName>
+ <xilinx:coreRevision>2</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>user.org:user:memstream_axi_wrapper:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2023-04-21T15:18:55Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="nopcore"/>
+ </xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8f86a494"/>
- <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5a080bee"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d633e93f"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="2e562330"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="134f154d"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="83e5a517"/>
+ <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="733f6ab8"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="b683eac1"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="113e465f"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4d679ad7"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="21f5114f"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="b48a7ddc"/>
+ <xilinx:targetDRCs>
+ <xilinx:targetDRC xilinx:tool="ipi">
+ <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl
deleted file mode 100644
index a68b85e1f5bdb3dc102f14eb4e3b8d82a86fa556..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl
+++ /dev/null
@@ -1,2 +0,0 @@
-# This file is automatically written. Do not modify.
-proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {MEM_DEPTH MEM_WIDTH } {expr 2+ceil(log($MEM_DEPTH*pow(2,ceil(log(($MEM_WIDTH+31)/32)/log(2))))/log(2))}
diff --git a/finn-rtllib/memstream/hdl/memstream.sv b/finn-rtllib/memstream/hdl/memstream.sv
new file mode 100644
index 0000000000000000000000000000000000000000..9cbef493a3e57f3c7e8caeb310d54281799ef6c9
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream.sv
@@ -0,0 +1,176 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream #(
+ int unsigned DEPTH,
+ int unsigned WIDTH,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto"
+)(
+ input logic clk,
+ input logic rst,
+
+ // Configuration and readback interface - compatible with ap_memory
+ input logic config_ce,
+ input logic config_we,
+ input logic [31 :0] config_address,
+ input logic [WIDTH-1:0] config_d0,
+
+ output logic config_rack,
+ output logic [WIDTH-1:0] config_q0,
+
+ // Continuous output stream
+ input logic ordy,
+ output logic ovld,
+ output logic [WIDTH-1:0] odat
+);
+
+ typedef logic [$clog2(DEPTH)-1:0] addr_t;
+ typedef logic [WIDTH -1:0] data_t;
+
+ uwire en; // Pipeline enable
+ uwire rollback; // Rollback stream reads if backpressure would block read back
+
+ // Counter with pre-computed last indication for val == DEPTH-1
+ typedef struct {
+ addr_t val;
+ logic lst;
+ } ptr_t;
+
+ // Counter history to facilitate pipeline rollback
+ ptr_t Ptr[3] = '{
+ 0: '{ val: 0, lst: DEPTH<2 },
+ default: '{ default: 'x }
+ };
+
+ //-----------------------------------------------------------------------
+ // Stage #0: Address & Op
+ logic Wr1 = 0; // Write
+ logic Rb1 = 0; // Read back
+ logic Rs1 = 0; // Read stream
+ data_t Data1 = 'x;
+ if(1) begin : blkStage1
+ // Increment for wrapping DEPTH-1 back to zero
+ localparam int unsigned WRAP_INC = 2**$bits(addr_t) - DEPTH + 1;
+
+ uwire ptr_t ptr_eff = rollback? Ptr[2] : Ptr[0];
+ uwire ptr_t ptr_nxt;
+ assign ptr_nxt.val = ptr_eff.val + (config_ce? 0 : !ptr_eff.lst? 1 : WRAP_INC);
+ assign ptr_nxt.lst =
+ DEPTH < 2? 1 :
+ config_ce? ptr_eff.lst :
+ ptr_eff.lst? 0 :
+ /* else */ ptr_eff.val == DEPTH-2;
+
+ always_ff @(posedge clk) begin
+ if(rst) Ptr[0] <= '{ val: 0, lst: DEPTH<2 };
+ else if(en) Ptr[0] <= ptr_nxt;
+ end
+
+ // Issue next Memory Operation
+ always_ff @(posedge clk) begin
+ if(rst) begin
+ Wr1 <= 0;
+ Rb1 <= 0;
+ Rs1 <= 0;
+ Ptr[1] <= '{ default : 'x };
+ Data1 <= 'x;
+ end
+ else if(en) begin
+ Wr1 <= 0;
+ Rb1 <= 0;
+ Rs1 <= 0;
+ if(config_ce) begin
+ if(config_we) Wr1 <= 1;
+ else Rb1 <= 1;
+ Ptr[1] <= '{ val: config_address, lst: 'x };
+ Data1 <= config_d0;
+ end
+ else begin
+ Rs1 <= 1;
+ Ptr[1] <= ptr_eff;
+ Data1 <= 'x;
+ end
+ end
+ end
+ end : blkStage1
+
+ //-----------------------------------------------------------------------
+ // Stage #2: Memory Access
+ logic Rb2 = 0;
+ logic Rs2 = 0;
+ data_t Data2 = 'x;
+ if(1) begin : blkStage2
+ (* RAM_STYLE = RAM_STYLE *)
+ data_t Mem[DEPTH];
+
+ // Optional Memory Initialization
+ if(INIT_FILE != "") initial $readmemh(INIT_FILE, Mem);
+
+ // Execute Memory Operation
+ uwire addr_t addr = Ptr[1].val;
+ always_ff @(posedge clk) begin
+ if(en) begin
+ if(Wr1) Mem[addr] <= Data1;
+ Data2 <= Mem[addr];
+ end
+ end
+
+ // Copy Output Designation
+ always_ff @(posedge clk) begin
+ if(rst) begin
+ Rb2 <= 0;
+ Rs2 <= 0;
+ Ptr[2] <= '{ default: 'x };
+ end
+ else if(en) begin
+ Rb2 <= Rb1;
+ Rs2 <= Rs1 && !rollback;
+ Ptr[2] <= Ptr[1];
+ end
+ end
+ end : blkStage2
+
+ //-----------------------------------------------------------------------
+ // Output Interfaces
+ assign config_rack = Rb2;
+ assign config_q0 = Data2;
+
+ assign ovld = Rs2;
+ assign odat = Data2;
+
+ uwire backpressure = Rs2 && !ordy;
+ assign rollback = backpressure && (Rb1 || config_ce);
+ assign en = !backpressure || Rb1 || config_ce;
+
+endmodule : memstream
diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v
deleted file mode 100644
index 2cd955f8d1ff0dd5dfed8b004df7053573a43488..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream.v
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module memstream
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 6,//1 up to 6
-
- parameter MEM_DEPTH = 13824,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
- parameter STRM2_WIDTH = 32,
- parameter STRM3_WIDTH = 32,
- parameter STRM4_WIDTH = 32,
- parameter STRM5_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 2304,
- parameter STRM1_DEPTH = 2304,
- parameter STRM2_DEPTH = 2304,
- parameter STRM3_DEPTH = 2304,
- parameter STRM4_DEPTH = 2304,
- parameter STRM5_DEPTH = 2304,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 2304,
- parameter STRM2_OFFSET = 4608,
- parameter STRM3_OFFSET = 6912,
- parameter STRM4_OFFSET = 9216,
- parameter STRM5_OFFSET = 11520,
-
- parameter AXILITE_ADDR_WIDTH = 2+$clog2(MEM_DEPTH*(1<<$clog2((MEM_WIDTH+31)/32)))
-)
-
-(
- input aclk,
- input aresetn,
-
- output awready,
- input awvalid,
- input [AXILITE_ADDR_WIDTH-1:0] awaddr,
- input [2:0] awprot,
- //write data
- output wready,
- input wvalid,
- input [31:0] wdata,
- input [3:0] wstrb,
- //burst response
- input bready,
- output bvalid,
- output [1:0] bresp,
-
- //Read channels
- //read address
- output arready,
- input arvalid,
- input [AXILITE_ADDR_WIDTH-1:0] araddr,
- input [2:0] arprot,
- //read data
- input rready,
- output rvalid,
- output [1:0] rresp,
- output [31:0] rdata,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_afull,
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_afull,
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
-
- input m_axis_2_afull,
- input m_axis_2_tready,
- output m_axis_2_tvalid,
- output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
-
- input m_axis_3_afull,
- input m_axis_3_tready,
- output m_axis_3_tvalid,
- output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
-
- input m_axis_4_afull,
- input m_axis_4_tready,
- output m_axis_4_tvalid,
- output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
-
- input m_axis_5_afull,
- input m_axis_5_tready,
- output m_axis_5_tvalid,
- output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
-
-
-);
-
-wire [31:0] config_address;
-wire config_ce;
-wire config_we;
-wire config_rack;
-wire [MEM_WIDTH-1:0] config_d0;
-wire [MEM_WIDTH-1:0] config_q0;
-
-generate
-if(NSTREAMS <= 2) begin: singleblock
-
-
-memstream_singleblock
-#(
- .CONFIG_EN(CONFIG_EN),
- .NSTREAMS(NSTREAMS),
- .MEM_DEPTH(MEM_DEPTH),
- .MEM_WIDTH(MEM_WIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE),
-
- //widths per stream
- .STRM0_WIDTH(STRM0_WIDTH),
- .STRM1_WIDTH(STRM1_WIDTH),
-
- //depths per stream
- .STRM0_DEPTH(STRM0_DEPTH),
- .STRM1_DEPTH(STRM1_DEPTH),
-
- //offsets for each stream
- .STRM0_OFFSET(STRM0_OFFSET),
- .STRM1_OFFSET(STRM1_OFFSET)
-)
-mem
-(
- .aclk(aclk),
- .aresetn(aresetn),
-
- .config_address(config_address),
- .config_ce(config_ce),
- .config_we(config_we),
- .config_d0(config_d0),
- .config_q0(config_q0),
- .config_rack(config_rack),
-
- .m_axis_0_tready(m_axis_0_tready),
- .m_axis_0_tvalid(m_axis_0_tvalid),
- .m_axis_0_tdata(m_axis_0_tdata),
-
- .m_axis_1_tready(m_axis_1_tready),
- .m_axis_1_tvalid(m_axis_1_tvalid),
- .m_axis_1_tdata(m_axis_1_tdata)
-);
-
-assign m_axis_2_tvalid = 0;
-assign m_axis_2_tdata = 0;
-assign m_axis_3_tvalid = 0;
-assign m_axis_3_tdata = 0;
-assign m_axis_4_tvalid = 0;
-assign m_axis_4_tdata = 0;
-assign m_axis_5_tvalid = 0;
-assign m_axis_5_tdata = 0;
-
-end else begin: multiblock
-
-
-memstream_multiblock
-#(
- .CONFIG_EN(CONFIG_EN),
- .NSTREAMS(NSTREAMS),
- .MEM_DEPTH(MEM_DEPTH),
- .MEM_WIDTH(MEM_WIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE),
-
- //widths per stream
- .STRM0_WIDTH(STRM0_WIDTH),
- .STRM1_WIDTH(STRM1_WIDTH),
- .STRM2_WIDTH(STRM2_WIDTH),
- .STRM3_WIDTH(STRM3_WIDTH),
- .STRM4_WIDTH(STRM4_WIDTH),
- .STRM5_WIDTH(STRM5_WIDTH),
-
- //depths per stream
- .STRM0_DEPTH(STRM0_DEPTH),
- .STRM1_DEPTH(STRM1_DEPTH),
- .STRM2_DEPTH(STRM2_DEPTH),
- .STRM3_DEPTH(STRM3_DEPTH),
- .STRM4_DEPTH(STRM4_DEPTH),
- .STRM5_DEPTH(STRM5_DEPTH),
-
- //offsets for each stream
- .STRM0_OFFSET(STRM0_OFFSET),
- .STRM1_OFFSET(STRM1_OFFSET),
- .STRM2_OFFSET(STRM2_OFFSET),
- .STRM3_OFFSET(STRM3_OFFSET),
- .STRM4_OFFSET(STRM4_OFFSET),
- .STRM5_OFFSET(STRM5_OFFSET)
-)
-mem
-(
- .aclk(aclk),
- .aresetn(aresetn),
-
- .config_address(config_address),
- .config_ce(config_ce),
- .config_we(config_we),
- .config_d0(config_d0),
- .config_q0(config_q0),
-
- .m_axis_0_afull(m_axis_0_afull),
- .m_axis_0_tready(m_axis_0_tready),
- .m_axis_0_tvalid(m_axis_0_tvalid),
- .m_axis_0_tdata(m_axis_0_tdata),
-
- .m_axis_1_afull(m_axis_1_afull),
- .m_axis_1_tready(m_axis_1_tready),
- .m_axis_1_tvalid(m_axis_1_tvalid),
- .m_axis_1_tdata(m_axis_1_tdata),
-
- .m_axis_2_afull(m_axis_2_afull),
- .m_axis_2_tready(m_axis_2_tready),
- .m_axis_2_tvalid(m_axis_2_tvalid),
- .m_axis_2_tdata(m_axis_2_tdata),
-
- .m_axis_3_afull(m_axis_3_afull),
- .m_axis_3_tready(m_axis_3_tready),
- .m_axis_3_tvalid(m_axis_3_tvalid),
- .m_axis_3_tdata(m_axis_3_tdata),
-
- .m_axis_4_afull(m_axis_4_afull),
- .m_axis_4_tready(m_axis_4_tready),
- .m_axis_4_tvalid(m_axis_4_tvalid),
- .m_axis_4_tdata(m_axis_4_tdata),
-
- .m_axis_5_afull(m_axis_5_afull),
- .m_axis_5_tready(m_axis_5_tready),
- .m_axis_5_tvalid(m_axis_5_tvalid),
- .m_axis_5_tdata(m_axis_5_tdata)
-
-);
-
-
-end
-endgenerate
-
-axi4lite_if
-#(
- .ADDR_WIDTH(AXILITE_ADDR_WIDTH),
- .DATA_WIDTH(32),
- .IP_DATA_WIDTH(MEM_WIDTH)
-)
-config_if
-(
- //system signals
- .aclk(aclk),
- .aresetn(aresetn),
-
- //Write channels
- //write address
- .awready(awready),
- .awvalid(awvalid),
- .awaddr(awaddr),
- .awprot(awprot),
- //write data
- .wready(wready),
- .wvalid(wvalid),
- .wdata(wdata),
- .wstrb(wstrb),
- //burst response
- .bready(bready),
- .bvalid(bvalid),
- .bresp(bresp),
-
- //Read channels
- //read address
- .arready(arready),
- .arvalid(arvalid),
- .araddr(araddr),
- .arprot(arprot),
- //read data
- .rready(rready),
- .rvalid(rvalid),
- .rresp(rresp),
- .rdata(rdata),
-
- //IP-side interface
- .ip_en(config_ce),
- .ip_wen(config_we),
- .ip_addr(config_address),
- .ip_wdata(config_d0),
- .ip_rack(config_rack),
- .ip_rdata(config_q0)
-);
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_axi.sv b/finn-rtllib/memstream/hdl/memstream_axi.sv
new file mode 100644
index 0000000000000000000000000000000000000000..136bcb1d7e5d28a56e84302346f97b4844ebf69a
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream_axi.sv
@@ -0,0 +1,136 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_axi #(
+ int unsigned DEPTH,
+ int unsigned WIDTH,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto",
+
+ localparam int unsigned AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
+)(
+ // Global Control
+ input logic clk,
+ input logic rst,
+
+ // AXI-lite Write
+ output logic awready,
+ input logic awvalid,
+ input logic [2:0] awprot,
+ input logic [AXILITE_ADDR_WIDTH-1:0] awaddr,
+
+ output logic wready,
+ input logic wvalid,
+ input logic [31:0] wdata,
+ input logic [ 3:0] wstrb,
+
+ input logic bready,
+ output logic bvalid,
+ output logic [1:0] bresp,
+
+ // AXI-lite Read
+ output logic arready,
+ input logic arvalid,
+ input logic [2:0] arprot,
+ input logic [AXILITE_ADDR_WIDTH-1:0] araddr,
+
+ input logic rready,
+ output logic rvalid,
+ output logic [ 1:0] rresp,
+ output logic [31:0] rdata,
+
+ // Continuous output stream
+ input logic m_axis_0_tready,
+ output logic m_axis_0_tvalid,
+ output logic [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata
+);
+
+ //-----------------------------------------------------------------------
+ // AXI-lite to ap_memory Adapter
+ uwire [31:0] config_address;
+ uwire config_ce;
+ uwire config_we;
+ uwire config_rack;
+ uwire [WIDTH-1:0] config_d0;
+ uwire [WIDTH-1:0] config_q0;
+ axi4lite_if #(
+ .ADDR_WIDTH(AXILITE_ADDR_WIDTH),
+ .DATA_WIDTH(32),
+ .IP_DATA_WIDTH(WIDTH)
+ ) config_if (
+ .aclk(clk), .aresetn(!rst),
+
+ // Write Channels
+ .awready, .awvalid, .awaddr, .awprot,
+ .wready, .wvalid, .wdata, .wstrb,
+ .bready, .bvalid, .bresp,
+
+ // Read Channels
+ .arready, .arvalid, .araddr, .arprot,
+ .rready, .rvalid, .rresp, .rdata,
+
+ // IP-side Interface
+ .ip_en(config_ce),
+ .ip_wen(config_we),
+ .ip_addr(config_address),
+ .ip_wdata(config_d0),
+ .ip_rack(config_rack),
+ .ip_rdata(config_q0)
+ );
+
+ //-----------------------------------------------------------------------
+ // Streaming Memory Backend
+ memstream #(
+ .DEPTH(DEPTH),
+ .WIDTH(WIDTH),
+ .INIT_FILE(INIT_FILE),
+ .RAM_STYLE(RAM_STYLE)
+ ) mem (
+ .clk, .rst,
+
+ .config_address,
+ .config_ce,
+ .config_we,
+ .config_d0,
+ .config_q0,
+ .config_rack,
+
+ .ordy(m_axis_0_tready),
+ .ovld(m_axis_0_tvalid),
+ .odat(m_axis_0_tdata[WIDTH-1:0])
+ );
+ if($bits(m_axis_0_tdata) > WIDTH) begin
+ assign m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] = '0;
+ end
+
+endmodule : memstream_axi
diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..69d6b64dec6376c07f9325ec152484a66393a04c
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
@@ -0,0 +1,122 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_axi_wrapper #(
+ parameter DEPTH = 512,
+ parameter WIDTH = 32,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto",
+
+ parameter AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
+)(
+ // Global Control
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *)
+ input ap_clk,
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *)
+ input ap_rst_n,
+
+ // AXI-lite Write
+ output awready,
+ input awvalid,
+ input [2:0] awprot,
+ input [AXILITE_ADDR_WIDTH-1:0] awaddr,
+
+ output wready,
+ input wvalid,
+ input [31:0] wdata,
+ input [ 3:0] wstrb,
+
+ input bready,
+ output bvalid,
+ output [1:0] bresp,
+
+ // AXI-lite Read
+ output arready,
+ input arvalid,
+ input [2:0] arprot,
+ input [AXILITE_ADDR_WIDTH-1:0] araddr,
+
+ input rready,
+ output rvalid,
+ output [ 1:0] rresp,
+ output [31:0] rdata,
+
+ // Continuous output stream
+ input m_axis_0_tready,
+ output m_axis_0_tvalid,
+ output [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata
+);
+
+ localparam INIT_FILTERED =
+`ifdef SYNTHESIS
+ RAM_STYLE == "ultra"? "" :
+`endif
+ INIT_FILE;
+
+ memstream_axi #(
+ .DEPTH(DEPTH), .WIDTH(WIDTH),
+ .INIT_FILE(INIT_FILTERED),
+ .RAM_STYLE(RAM_STYLE)
+ ) core (
+ .clk(ap_clk), .rst(!ap_rst_n),
+
+ // AXI-lite Write
+ .awready(awready),
+ .awvalid(awvalid),
+ .awprot(awprot),
+ .awaddr(awaddr),
+ .wready(wready),
+ .wvalid(wvalid),
+ .wdata(wdata),
+ .wstrb(wstrb),
+ .bready(bready),
+ .bvalid(bvalid),
+ .bresp(bresp),
+
+ // AXI-lite Read
+ .arready(arready),
+ .arvalid(arvalid),
+ .arprot(arprot),
+ .araddr(araddr),
+ .rready(rready),
+ .rvalid(rvalid),
+ .rresp(rresp),
+ .rdata(rdata),
+
+ // Continuous output stream
+ .m_axis_0_tready(m_axis_0_tready),
+ .m_axis_0_tvalid(m_axis_0_tvalid),
+ .m_axis_0_tdata(m_axis_0_tdata)
+ );
+
+endmodule : memstream_axi_wrapper
diff --git a/finn-rtllib/memstream/hdl/memstream_multiblock.v b/finn-rtllib/memstream/hdl/memstream_multiblock.v
deleted file mode 100644
index 4e6167132da119d9e19a5f4b6a378311e74311c3..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream_multiblock.v
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module memstream_multiblock
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 6,//1 up to 6
-
- parameter MEM_DEPTH = 13824,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
- parameter STRM2_WIDTH = 32,
- parameter STRM3_WIDTH = 32,
- parameter STRM4_WIDTH = 32,
- parameter STRM5_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 2304,
- parameter STRM1_DEPTH = 2304,
- parameter STRM2_DEPTH = 2304,
- parameter STRM3_DEPTH = 2304,
- parameter STRM4_DEPTH = 2304,
- parameter STRM5_DEPTH = 2304,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 2304,
- parameter STRM2_OFFSET = 4608,
- parameter STRM3_OFFSET = 6912,
- parameter STRM4_OFFSET = 9216,
- parameter STRM5_OFFSET = 11520
-)
-
-(
- input aclk,
- input aresetn,
-
- //optional configuration interface compatible with ap_memory
- input [31:0] config_address,
- input config_ce,
- input config_we,
- input [31:0] config_d0,
- output [31:0] config_q0,
- output config_rack,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_afull,
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_afull,
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
-
- input m_axis_2_afull,
- input m_axis_2_tready,
- output m_axis_2_tvalid,
- output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
-
- input m_axis_3_afull,
- input m_axis_3_tready,
- output m_axis_3_tvalid,
- output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
-
- input m_axis_4_afull,
- input m_axis_4_tready,
- output m_axis_4_tvalid,
- output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
-
- input m_axis_5_afull,
- input m_axis_5_tready,
- output m_axis_5_tvalid,
- output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
-
-
-);
-
-//calculate number of RAMB18 blocks we need depth-wise
-localparam NMEMBLOCKS = (MEM_DEPTH+1023) / 1024; //ceil(MEM_DEPTH/1024)
-
-//calculate width of address for each block
-localparam BLOCKADRWIDTH = NMEMBLOCKS > 1 ? 10 : $clog2(MEM_DEPTH);
-
-//determine whether a stream needs to multiplex between memory blocks
-localparam STRM0_MUX = ((STRM0_OFFSET/1024) != ((STRM0_OFFSET+STRM0_DEPTH)/1024));
-localparam STRM1_MUX = ((STRM1_OFFSET/1024) != ((STRM1_OFFSET+STRM1_DEPTH)/1024));
-localparam STRM2_MUX = ((STRM2_OFFSET/1024) != ((STRM2_OFFSET+STRM2_DEPTH)/1024));
-localparam STRM3_MUX = ((STRM3_OFFSET/1024) != ((STRM3_OFFSET+STRM3_DEPTH)/1024));
-localparam STRM4_MUX = ((STRM4_OFFSET/1024) != ((STRM4_OFFSET+STRM4_DEPTH)/1024));
-localparam STRM5_MUX = ((STRM5_OFFSET/1024) != ((STRM5_OFFSET+STRM5_DEPTH)/1024));
-
-//determine what the base block of each stream is
-localparam STRM0_BLOCK = (STRM0_OFFSET/1024);
-localparam STRM1_BLOCK = (STRM1_OFFSET/1024);
-localparam STRM2_BLOCK = (STRM2_OFFSET/1024);
-localparam STRM3_BLOCK = (STRM3_OFFSET/1024);
-localparam STRM4_BLOCK = (STRM4_OFFSET/1024);
-localparam STRM5_BLOCK = (STRM5_OFFSET/1024);
-
-//determine what the end block of each stream is
-localparam STRM0_END_BLOCK = ((STRM0_OFFSET+STRM0_DEPTH-1)/1024);
-localparam STRM1_END_BLOCK = ((STRM1_OFFSET+STRM1_DEPTH-1)/1024);
-localparam STRM2_END_BLOCK = ((STRM2_OFFSET+STRM2_DEPTH-1)/1024);
-localparam STRM3_END_BLOCK = ((STRM3_OFFSET+STRM3_DEPTH-1)/1024);
-localparam STRM4_END_BLOCK = ((STRM4_OFFSET+STRM4_DEPTH-1)/1024);
-localparam STRM5_END_BLOCK = ((STRM5_OFFSET+STRM5_DEPTH-1)/1024);
-
-//determine the number of blocks spanned by each stream
-localparam STRM0_NBLOCKS = STRM0_END_BLOCK - STRM0_BLOCK + 1;
-localparam STRM1_NBLOCKS = STRM1_END_BLOCK - STRM1_BLOCK + 1;
-localparam STRM2_NBLOCKS = STRM2_END_BLOCK - STRM2_BLOCK + 1;
-localparam STRM3_NBLOCKS = STRM3_END_BLOCK - STRM3_BLOCK + 1;
-localparam STRM4_NBLOCKS = STRM4_END_BLOCK - STRM4_BLOCK + 1;
-localparam STRM5_NBLOCKS = STRM5_END_BLOCK - STRM5_BLOCK + 1;
-
-//TODO: check that memory width is equal to the widest stream
-//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
-initial begin
- if((NSTREAMS < 1) | (NSTREAMS > 6)) begin
- $display("Invalid setting for NSTREAMS, please set in range [1,6]");
- $finish();
- end
-end
-
-//invert reset
-wire rst;
-assign rst = ~aresetn;
-
-//WARNING: pipeline depth is larger than the number of streams per port so we have in-flight writes that may see not-ready when they get executed
-//solution: use prog-full to make sure we have an equal number of free slots in the stream to the read pipeline depth
-
-reg [$clog2(MEM_DEPTH)-1:0] strm0_addr = STRM0_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm1_addr = STRM1_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm2_addr = STRM2_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm3_addr = STRM3_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm4_addr = STRM4_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm5_addr = STRM5_OFFSET;
-
-reg strm0_incr_en;
-reg strm1_incr_en;
-reg strm2_incr_en;
-reg strm3_incr_en;
-reg strm4_incr_en;
-reg strm5_incr_en;
-
-wire strm0_rst;
-wire strm1_rst;
-wire strm2_rst;
-wire strm3_rst;
-wire strm4_rst;
-wire strm5_rst;
-
-reg strm0_ready;
-reg strm1_ready;
-reg strm2_ready;
-reg strm3_ready;
-reg strm4_ready;
-reg strm5_ready;
-
-//arbiter: work on one stream at a time
-//multiplex each port between (up to) half of the streams
-reg [1:0] current_stream_porta = 0;
-reg [1:0] current_stream_portb = 0;
-
-always @(posedge aclk) begin
- if(rst)
- current_stream_porta <= 0;
- else case(current_stream_porta)
- 0: current_stream_porta <= strm2_ready ? 1 : strm4_ready ? 2 : 0;
- 1: current_stream_porta <= strm4_ready ? 2 : strm0_ready ? 0 : 1;
- 2: current_stream_porta <= strm0_ready ? 0 : strm2_ready ? 1 : 2;
- endcase
- if(rst)
- current_stream_portb <= 0;
- else case(current_stream_portb)
- 0: current_stream_portb <= strm3_ready ? 1 : strm5_ready ? 2 : 0;
- 1: current_stream_portb <= strm5_ready ? 2 : strm1_ready ? 0 : 1;
- 2: current_stream_portb <= strm1_ready ? 0 : strm3_ready ? 1 : 2;
- endcase
-end
-
-always @(posedge aclk) begin
- if(rst) begin
- strm0_incr_en <= 0;
- strm1_incr_en <= 0;
- strm2_incr_en <= 0;
- strm3_incr_en <= 0;
- strm4_incr_en <= 0;
- strm5_incr_en <= 0;
- end else begin
- strm0_incr_en <= (current_stream_porta == 0) & strm0_ready;
- strm1_incr_en <= (current_stream_portb == 0) & strm1_ready;
- strm2_incr_en <= (current_stream_porta == 1) & strm2_ready;
- strm3_incr_en <= (current_stream_portb == 1) & strm3_ready;
- strm4_incr_en <= (current_stream_porta == 2) & strm4_ready;
- strm5_incr_en <= (current_stream_portb == 2) & strm5_ready;
- end
-end
-
-assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
-assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
-assign strm2_rst = strm2_incr_en & (strm2_addr == (STRM2_OFFSET + STRM2_DEPTH-1));
-assign strm3_rst = strm3_incr_en & (strm3_addr == (STRM3_OFFSET + STRM3_DEPTH-1));
-assign strm4_rst = strm4_incr_en & (strm4_addr == (STRM4_OFFSET + STRM4_DEPTH-1));
-assign strm5_rst = strm5_incr_en & (strm5_addr == (STRM5_OFFSET + STRM5_DEPTH-1));
-
-always @(posedge aclk) begin
- strm0_ready <= ~m_axis_0_afull;
- strm1_ready <= ~m_axis_1_afull & (NSTREAMS >= 2);
- strm2_ready <= ~m_axis_2_afull & (NSTREAMS >= 3);
- strm3_ready <= ~m_axis_3_afull & (NSTREAMS >= 4);
- strm4_ready <= ~m_axis_4_afull & (NSTREAMS >= 5);
- strm5_ready <= ~m_axis_5_afull & (NSTREAMS >= 6);
-end
-
-//one address counter per stream; more LUTs but keeps routing short and local
-always @(posedge aclk) begin
- if(strm0_rst | rst)
- strm0_addr <= STRM0_OFFSET;
- else if(strm0_incr_en)
- strm0_addr <= strm0_addr + 1;
- if(strm1_rst | rst)
- strm1_addr <= STRM1_OFFSET;
- else if(strm1_incr_en)
- strm1_addr <= strm1_addr + 1;
- if(strm2_rst | rst)
- strm2_addr <= STRM2_OFFSET;
- else if(strm2_incr_en)
- strm2_addr <= strm2_addr + 1;
- if(strm3_rst | rst)
- strm3_addr <= STRM3_OFFSET;
- else if(strm3_incr_en)
- strm3_addr <= strm3_addr + 1;
- if(strm4_rst | rst)
- strm4_addr <= STRM4_OFFSET;
- else if(strm4_incr_en)
- strm4_addr <= strm4_addr + 1;
- if(strm5_rst | rst)
- strm5_addr <= STRM5_OFFSET;
- else if(strm5_incr_en)
- strm5_addr <= strm5_addr + 1;
-end
-
-reg [$clog2(MEM_DEPTH)-1:0] addra;
-wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqa;
-
-reg [$clog2(MEM_DEPTH)-1:0] addrb;
-wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqb;
-
-wire [NMEMBLOCKS-1:0] we;
-
-reg [1:0] addr_select_porta;
-reg [1:0] addr_select_portb;
-
-//multiplex addresses of various streams into address ports of memory
-always @(posedge aclk) begin
- addr_select_porta <= current_stream_porta;
- case(addr_select_porta)
- 0: addra <= strm0_addr;
- 1: addra <= strm2_addr;
- 2: addra <= strm4_addr;
- endcase
- addr_select_portb <= current_stream_portb;
- case(addr_select_portb)
- 0: addrb <= strm1_addr;
- 1: addrb <= strm3_addr;
- 2: addrb <= strm5_addr;
- endcase
-end
-
-genvar g;
-generate for(g=0; g<NMEMBLOCKS; g=g+1) begin: blockports
-
-assign we[g] = (CONFIG_EN == 1) & config_ce & config_we & (config_address[31:BLOCKADRWIDTH] == g);
-
-ramb18_wf_dualport
-#(
- .ID(g),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .wea(we[g]),
- .ena(1'b1),
- .enqa(1'b1),
- .addra(we[g] ? config_address[BLOCKADRWIDTH-1:0] : addra[BLOCKADRWIDTH-1:0]),
- .wdataa(config_d0),
- .rdqa(rdqa[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH]),
-
- .web(1'b0),
- .enb(1'b1),
- .enqb(1'b1),
- .addrb(addrb[BLOCKADRWIDTH-1:0]),
- .wdatab('d0),
- .rdqb(rdqb[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH])
-);
-
-end
-endgenerate
-
-integer i;
-
-generate if(NMEMBLOCKS > 1) begin: multiblock
-
-wire [MEM_WIDTH-1:0] rdqmux[5:0];
-
-reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblocka[2:0];
-reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblockb[2:0];
-
-always @(posedge aclk) begin
- rdblocka[0] <= addra[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
- rdblockb[0] <= addrb[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
- for(i=0; i<2; i=i+1) begin
- rdblocka[i+1] <= rdblocka[i];
- rdblockb[i+1] <= rdblockb[i];
- end
-end
-
-if(NSTREAMS >= 1) begin: en_strm0
- if(STRM0_MUX == 1) begin: mux0
- mux #(STRM0_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM0_BLOCK+STRM0_NBLOCKS)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH],rdqmux[0],rdblocka[1] - STRM0_BLOCK);
- end else begin: nomux0
- assign rdqmux[0] = rdqa[(STRM0_BLOCK+1)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH];
- end
- assign m_axis_0_tdata = rdqmux[0][STRM0_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 2) begin: en_strm1
- if(STRM1_MUX == 1) begin: mux1
- mux #(STRM1_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM1_BLOCK+STRM1_NBLOCKS)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH],rdqmux[1],rdblockb[1] - STRM1_BLOCK);
- end else begin: nomux1
- assign rdqmux[1] = rdqb[(STRM1_BLOCK+1)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH];
- end
- assign m_axis_1_tdata = rdqmux[1][STRM1_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 3) begin: en_strm2
- if(STRM2_MUX == 1) begin: mux2
- mux #(STRM2_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM2_BLOCK+STRM2_NBLOCKS)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH],rdqmux[2],rdblocka[1] - STRM2_BLOCK);
- end else begin: nomux2
- assign rdqmux[2] = rdqa[(STRM2_BLOCK+1)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH];
- end
- assign m_axis_2_tdata = rdqmux[2][STRM2_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 4) begin: en_strm3
- if(STRM3_MUX == 1) begin: mux3
- mux #(STRM3_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM3_BLOCK+STRM3_NBLOCKS)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH],rdqmux[3],rdblockb[1] - STRM3_BLOCK);
- end else begin: nomux3
- assign rdqmux[3] = rdqb[(STRM3_BLOCK+1)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH];
- end
- assign m_axis_3_tdata = rdqmux[3][STRM3_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 5) begin: en_strm4
- if(STRM4_MUX == 1) begin: mux4
- mux #(STRM4_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM4_BLOCK+STRM4_NBLOCKS)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH],rdqmux[4],rdblocka[1] - STRM4_BLOCK);
- end else begin: nomux4
- assign rdqmux[4] = rdqa[(STRM4_BLOCK+1)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH];
- end
- assign m_axis_4_tdata = rdqmux[4][STRM4_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 6) begin: en_strm5
- if(STRM5_MUX == 1) begin: mux5
- mux #(STRM5_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM5_BLOCK+STRM5_NBLOCKS)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH],rdqmux[5],rdblockb[1] - STRM5_BLOCK);
- end else begin: nomux5
- assign rdqmux[5] = rdqb[(STRM5_BLOCK+1)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH];
- end
- assign m_axis_5_tdata = rdqmux[5][STRM5_WIDTH-1:0];
-end
-
-end else begin: singleblock
-
-if(NSTREAMS >= 1) begin: en_strm0_direct
- assign m_axis_0_tdata = rdqa[STRM0_WIDTH-1:0];
-end
-if(NSTREAMS >= 2) begin: en_strm1_direct
- assign m_axis_1_tdata = rdqb[STRM1_WIDTH-1:0];
-end
-if(NSTREAMS >= 3) begin: en_strm2_direct
- assign m_axis_2_tdata = rdqa[STRM2_WIDTH-1:0];
-end
-if(NSTREAMS >= 4) begin: en_strm3_direct
- assign m_axis_3_tdata = rdqb[STRM3_WIDTH-1:0];
-end
-if(NSTREAMS >= 5) begin: en_strm4_direct
- assign m_axis_4_tdata = rdqa[STRM4_WIDTH-1:0];
-end
-if(NSTREAMS >= 6) begin: en_strm5_direct
- assign m_axis_5_tdata = rdqb[STRM5_WIDTH-1:0];
-end
-
-end
-endgenerate
-
-//output to AXI Streams
-reg tvalid_pipe0[2:0];
-reg tvalid_pipe1[2:0];
-reg tvalid_pipe2[2:0];
-reg tvalid_pipe3[2:0];
-reg tvalid_pipe4[2:0];
-reg tvalid_pipe5[2:0];
-
-assign m_axis_0_tvalid = tvalid_pipe0[2];
-assign m_axis_1_tvalid = tvalid_pipe1[2];
-assign m_axis_2_tvalid = tvalid_pipe2[2];
-assign m_axis_3_tvalid = tvalid_pipe3[2];
-assign m_axis_4_tvalid = tvalid_pipe4[2];
-assign m_axis_5_tvalid = tvalid_pipe5[2];
-
-
-always @(posedge aclk) begin
- tvalid_pipe0[0] <= strm0_incr_en;
- tvalid_pipe1[0] <= strm1_incr_en;
- tvalid_pipe2[0] <= strm2_incr_en;
- tvalid_pipe3[0] <= strm3_incr_en;
- tvalid_pipe4[0] <= strm4_incr_en;
- tvalid_pipe5[0] <= strm5_incr_en;
- for(i=0; i<2; i=i+1) begin: srl
- tvalid_pipe0[i+1] <= tvalid_pipe0[i];
- tvalid_pipe1[i+1] <= tvalid_pipe1[i];
- tvalid_pipe2[i+1] <= tvalid_pipe2[i];
- tvalid_pipe3[i+1] <= tvalid_pipe3[i];
- tvalid_pipe4[i+1] <= tvalid_pipe4[i];
- tvalid_pipe5[i+1] <= tvalid_pipe5[i];
- end
-end
-
-//dummy read, for now
-assign config_q0 = 0;
-assign config_rack = config_ce & ~config_we;
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_singleblock.v b/finn-rtllib/memstream/hdl/memstream_singleblock.v
deleted file mode 100644
index c9b8770aaa58dc3355bc259e5c5fece702125490..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream_singleblock.v
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- Implements a lightweight streamer for up to 2 streams in a single block of memory
-*/
-
-module memstream_singleblock
-#(
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 2,//1 up to 2
-
- parameter MEM_DEPTH = 512,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 256,
- parameter STRM1_DEPTH = 256,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 256
-)
-
-(
- input aclk,
- input aresetn,
-
- //optional configuration interface compatible with ap_memory
- input [31:0] config_address,
- input config_ce,
- input config_we,
- input [MEM_WIDTH-1:0] config_d0,
- output [MEM_WIDTH-1:0] config_q0,
- output config_rack,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata
-
-);
-
-
-//TODO: check that memory width is equal to the widest stream
-//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
-initial begin
- if((NSTREAMS < 1) | (NSTREAMS > 2)) begin
- $display("Invalid setting for NSTREAMS, please set in range [1,2]");
- $finish();
- end
-end
-
-//invert reset
-wire rst;
-assign rst = ~aresetn;
-
-wire strm0_incr_en;
-wire strm1_incr_en;
-
-assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid;
-assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid;
-
-reg rack_shift[1:0];
-
-generate
-if(MEM_DEPTH > 1) begin: use_ram
-
-//calculate width of memory address, with a minimum of 1 bit
-localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH);
-
-reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET;
-wire strm0_rst;
-assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
-
-//one address counter per stream; more LUTs but keeps routing short and local
-always @(posedge aclk) begin
- if(strm0_rst | rst)
- strm0_addr <= STRM0_OFFSET;
- else if(strm0_incr_en)
- strm0_addr <= strm0_addr + 1;
-end
-
-if(NSTREAMS == 1) begin: sdp
-
-ramb18_sdp
-#(
- .ID(0),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .DEPTH(MEM_DEPTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .ena(config_ce),
- .wea(config_we),
- .addra(config_address[BLOCKADRWIDTH-1:0]),
- .wdataa(config_d0),
-
- .enb(strm0_incr_en | config_ce),
- .enqb(strm0_incr_en | rack_shift[0]),
- .addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
- .rdqb(m_axis_0_tdata)
-);
-
-
-end else begin: tdp
-
-reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
-wire strm1_rst;
-assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
-
-always @(posedge aclk) begin
- if(strm1_rst | rst)
- strm1_addr <= STRM1_OFFSET;
- else if(strm1_incr_en)
- strm1_addr <= strm1_addr + 1;
-end
-
-ramb18_wf_dualport
-#(
- .ID(0),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .DEPTH(MEM_DEPTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .wea(config_we),
- .ena(strm0_incr_en | config_ce),
- .enqa(strm0_incr_en | config_ce_r),
- .addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
- .wdataa(config_d0),
- .rdqa(m_axis_0_tdata),
-
- .web(1'b0),
- .enb(strm1_incr_en),
- .enqb(strm1_incr_en),
- .addrb(strm1_addr),
- .wdatab('d0),
- .rdqb(m_axis_1_tdata)
-);
-
-end
-
-end else begin: bypass
-
-reg [MEM_WIDTH-1:0] singleval[0:0];
-initial begin
- `ifdef SYNTHESIS
- $readmemh({MEM_INIT,"memblock_synth_0.dat"}, singleval, 0, 0);
- `else
- $readmemh({MEM_INIT,"memblock_sim_0.dat"}, singleval, 0, 0);
- `endif
-end
-
-always @(posedge aclk)
- if(config_ce & config_we)
- singleval[0] <= config_d0;
-
-assign m_axis_0_tdata = singleval[0];
-assign m_axis_1_tdata = singleval[0];
-
-end
-endgenerate
-
-//signal valid after 2 tready cycles after initialization
-//then stay valid
-reg [1:0] tvalid_pipe0 = 2'd0;
-reg [1:0] tvalid_pipe1 = 2'd0;
-
-assign m_axis_0_tvalid = tvalid_pipe0[1];
-assign m_axis_1_tvalid = tvalid_pipe1[1];
-
-always @(posedge aclk) begin
- if(rst) begin
- tvalid_pipe0 <= 0;
- end else if(strm0_incr_en) begin
- tvalid_pipe0[0] <= 1;
- tvalid_pipe0[1] <= tvalid_pipe0[0];
- end
-end
-
-always @(posedge aclk) begin
- if(rst) begin
- tvalid_pipe1 <= 0;
- end else if(strm1_incr_en) begin
- tvalid_pipe1[0] <= 1;
- tvalid_pipe1[1] <= tvalid_pipe1[0];
- end
-end
-
-always @(posedge aclk) begin
- rack_shift[0] <= config_ce & ~config_we;
- rack_shift[1] <= rack_shift[0];
-end
-
-assign config_rack = rack_shift[1];
-assign config_q0 = m_axis_0_tdata;
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/mux.v b/finn-rtllib/memstream/hdl/mux.v
deleted file mode 100644
index f7087f9735771a73aa532ae19baf18569e9de663..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/mux.v
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module mux
-#(
- parameter NINPUTS = 1,
- parameter WIDTH = 16
-)
-(
- input [NINPUTS*WIDTH-1:0] in,
- output [WIDTH-1:0] out,
- input [$clog2(NINPUTS)-1:0] sel
-);
-
-assign out = in >> (sel*WIDTH);
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/ramb18_sdp.v b/finn-rtllib/memstream/hdl/ramb18_sdp.v
deleted file mode 100644
index 8d2fbf9a988c0e9702e1ed83f2b4e79efb1c5a85..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/ramb18_sdp.v
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module ramb18_sdp
-#(
- parameter ID = 0,
- parameter DWIDTH = 18,
- parameter AWIDTH = 10,
- parameter DEPTH = 2**AWIDTH,
- parameter MEM_INIT = "",
- parameter RAM_STYLE = "auto"
-)
-(
- input clk,
-
- input ena,
- input wea,
- input [AWIDTH-1:0] addra,
- input [DWIDTH-1:0] wdataa,
-
- input enb,
- input enqb,
- input [AWIDTH-1:0] addrb,
- output reg [DWIDTH-1:0] rdqb
-);
-
-(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1];
-reg [DWIDTH-1:0] rdatab;
-
-`ifdef SYNTHESIS
-reg [7:0] idx = ID;
-`else
-reg [15:0] idx;
-`endif
-
-//initialize memory
-initial begin
- //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
- //ID can go up to 99
- if (ID < 0 && ID > 99) begin
- $display("ID out of range [0-99]");
- $finish();
- end
- //MEM_INIT path must be terminated by /
- `ifdef SYNTHESIS
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_synth_",idx+8'd48,".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_synth_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1);
- `else
- $sformat(idx,"%0d",ID);
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_sim_",idx[7:0],".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_sim_",idx,".dat"}, mem, 0, DEPTH-1);
- `endif
-end
-
-//memory ports, with output pipeline register
-always @(posedge clk) begin
- if(wea)
- mem[addra] <= wdataa;
- if(enb)
- rdatab <= mem[addrb];
- if(enqb)
- rdqb <= rdatab;
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v b/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
deleted file mode 100644
index c7850106ae4cad21f1230477ee86062411e531c8..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module ramb18_wf_dualport
-#(
- parameter ID = 0,
- parameter DWIDTH = 18,
- parameter AWIDTH = 10,
- parameter DEPTH = 2**AWIDTH,
- parameter MEM_INIT = "",
- parameter RAM_STYLE = "auto"
-)
-(
- input clk,
-
- input wea,
- input ena,
- input enqa,
- input [AWIDTH-1:0] addra,
- input [DWIDTH-1:0] wdataa,
- output reg [DWIDTH-1:0] rdqa,
-
- input web,
- input enb,
- input enqb,
- input [AWIDTH-1:0] addrb,
- input [DWIDTH-1:0] wdatab,
- output reg [DWIDTH-1:0] rdqb
-);
-
-(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1];
-reg [DWIDTH-1:0] rdataa;
-reg [DWIDTH-1:0] rdatab;
-
-`ifdef SYNTHESIS
-reg [7:0] idx = ID;
-`else
-reg [15:0] idx;
-`endif
-
-//initialize memory
-initial begin
- //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
- //ID can go up to 99
- if (ID < 0 && ID > 99) begin
- $display("ID out of range [0-99]");
- $finish();
- end
- //MEM_INIT path must be terminated by /
- `ifdef SYNTHESIS
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1);
- `else
- $sformat(idx,"%0d",ID);
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_",idx[7:0],".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_",idx,".dat"}, mem, 0, DEPTH-1);
- `endif
-end
-
-//memory ports, with output pipeline register
-always @(posedge clk) begin
- if(ena) begin
- if(wea)
- mem[addra] <= wdataa;
- rdataa <= mem[addra];
- end
- if(enqa)
- rdqa <= rdataa;
-end
-always @(posedge clk) begin
- if(enb) begin
- if(web)
- mem[addrb] <= wdatab;
- rdatab <= mem[addrb];
- end
- if(enqb)
- rdqb <= rdatab;
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/gen_memblocks.sh b/finn-rtllib/memstream/sim/gen_memblocks.sh
deleted file mode 100644
index b6e6b656ad1ea7846666108a1d4b79eae295490f..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/gen_memblocks.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-NLINES=`cat $1 | wc -l`
-NBLOCKS=$(( ($NLINES + 1023) / 1024 ))
-rm memblock_*.dat
-
-for (( i=0; i<$NBLOCKS; i++ ))
-do
- START=$(( 1 + $i * 1024 ))
- tail -n +$START $1 | head -n 1024 >> memblock_$i.dat
-done
diff --git a/finn-rtllib/memstream/sim/golden.dat b/finn-rtllib/memstream/sim/golden.dat
deleted file mode 100644
index 1466271bcab961f742e242aea4241a4ffad02828..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/golden.dat
+++ /dev/null
@@ -1,9216 +0,0 @@
-AFB2B66A
-BB100CFF
-1ED93E9B
-1B8E800D
-DA9E0150
-38B1C916
-93BC4E64
-860F8373
-B31D708B
-C2934023
-739C9593
-4C898A3D
-CCC8F4C5
-8FA275E6
-47732CC7
-6857ABF0
-31671013
-6BC4AA43
-73D4F790
-2C6158B6
-FDC3B5D
-6DC755F2
-E0E7E8C9
-7862E17
-3D4FFE1E
-9AFFF447
-C862FD7D
-A4C4D89A
-D7D6EF51
-10E5A31D
-79DA9C63
-A83060A8
-EA988813
-6B411BCF
-85544B5A
-5AC91DE6
-586E6779
-8FE8161B
-4C57CC92
-74C918A6
-36B20D44
-5CB62FC0
-62FDB2E1
-4B1CB514
-526B7CEC
-B3FA61D0
-C95DDBE
-CC2BA600
-2466CD1D
-3354A056
-CCED3EAC
-6FFA09EE
-F9648FAF
-18CB5358
-EA506270
-66F385A6
-5B0246E5
-26218A76
-BC7CECFD
-5969F6FF
-3DAF5901
-C53D05BD
-1EDA2D76
-5C0C0010
-7A6C0C8C
-BF99E997
-C964C884
-4DE417F4
-8637312
-133B8C3A
-D637DB88
-297288F6
-CF1D00B3
-426BD0F3
-4D258120
-8F7EC898
-E15482D9
-DFDFC442
-16A5C4AE
-7A6A14DF
-5E9C2807
-31BD3EA2
-BD6DCDBC
-E47CD35E
-FA4FE42
-CCDE0036
-345EBCB7
-64686255
-AE1D77EB
-D2B42B84
-CD5E5824
-8DABAB1F
-4E07FFCA
-7F3B4C13
-1A62C962
-CE08835F
-E8E05318
-DC25C7BF
-132E4308
-5D0122D6
-B7451ACE
-829D2507
-19329C7F
-39FCA8F0
-DCD1A574
-17E2EEE
-B2B6583A
-2181E65
-7013A2A7
-46535CDE
-C85BF5D3
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diff --git a/finn-rtllib/memstream/sim/memstream_tb.sv b/finn-rtllib/memstream/sim/memstream_tb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4b2e850415e88fdf820931e2d6b75f6aac2f7267
--- /dev/null
+++ b/finn-rtllib/memstream/sim/memstream_tb.sv
@@ -0,0 +1,212 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_tb;
+ localparam int unsigned DEPTH = 256;
+ localparam int unsigned DATA_WIDTH = 32;
+
+ // Global Control
+ logic clk = 0;
+ always #5ns clk = !clk;
+ logic rst;
+
+ // Configuration Interface
+ logic [31:0] config_address;
+ logic config_ce;
+ logic config_we;
+ logic [DATA_WIDTH-1:0] config_d0;
+ uwire config_rack;
+ uwire [DATA_WIDTH-1:0] config_q0;
+
+ // Streamed Output
+ logic ordy;
+ uwire ovld;
+ uwire [DATA_WIDTH-1:0] odat;
+
+ initial begin
+ config_address = 'x;
+ config_ce = 0;
+ config_we = 0;
+ config_d0 = 'x;
+
+ ordy = 0;
+
+ rst = 1;
+ repeat(16) @(posedge clk);
+ rst <= 0;
+
+ // Write Parameters
+ config_ce <= 1;
+ config_we <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ config_address <= i;
+ config_d0 <= i;
+ @(posedge clk);
+ end
+ config_address <= 'x;
+ config_ce <= 0;
+ config_we <= 0;
+ config_d0 <= 'x;
+
+ rst <= 1;
+ @(posedge clk);
+ rst <= 0;
+
+ // One Round of Stream Read
+ ordy <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ @(posedge clk iff ovld);
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+ ordy <= 0;
+
+ // Full Parameter Readback
+ if(1) begin
+ automatic logic [DATA_WIDTH-1:0] Q[$] = {};
+
+ config_ce <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ config_address <= i;
+ @(posedge clk);
+ Q.push_back(i);
+
+ if(config_rack) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+ config_address <= 'x;
+ config_ce <= 0;
+
+ while(Q.size) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+
+ @(posedge clk iff config_rack);
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+
+ repeat(6) @(posedge clk);
+
+ // Another Round of Stream Read
+ ordy <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ @(posedge clk iff ovld);
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+ ordy <= 0;
+
+ // A Round of Stream Read with intermittent Read Backs
+ if(1) begin
+ automatic logic [DATA_WIDTH-1:0] Q[$] = {};
+
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ do begin
+ // Randomly delayed Readiness
+ if($urandom()%5 != 0) ordy <= 1;
+
+ // Issue and Check Random Read Backs
+ if($urandom()%9 == 0) begin
+ automatic int unsigned addr = $urandom() % DEPTH;
+ config_ce <= 1;
+ config_address <= addr;
+ Q.push_back(addr);
+ end
+ @(posedge clk);
+ config_ce <= 0;
+ config_address <= 'x;
+
+ if(config_rack) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+
+ end while(!ovld || !ordy);
+ ordy <= 0;
+
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+
+ while(Q.size) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+
+ @(posedge clk iff config_rack);
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+ ordy <= 0;
+
+ repeat(2) @(posedge clk);
+ $display("Test completed.");
+ $finish;
+ end
+
+ memstream #(
+ .DEPTH(DEPTH),
+ .WIDTH(DATA_WIDTH)
+ ) dut (
+ .clk, .rst,
+
+ .config_address,
+ .config_ce,
+ .config_we,
+ .config_d0,
+ .config_q0,
+ .config_rack,
+
+ .ordy,
+ .ovld,
+ .odat
+ );
+
+endmodule : memstream_tb
diff --git a/finn-rtllib/memstream/sim/tb_memstream.v b/finn-rtllib/memstream/sim/tb_memstream.v
deleted file mode 100644
index ad3efad5bd70c37a860ddb0ec5bff1c2e72c15f0..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/tb_memstream.v
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`timescale 1ns/10ps
-
-module tb_memstream;
-
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
-parameter CONFIG_EN = 1;
-parameter NSTREAMS = 4;//1 up to 6
-
-parameter MEM_DEPTH = 9216;
-parameter MEM_WIDTH = 32;
-parameter MEM_INIT = "./";
-parameter MEM_CHECK = "golden.dat";
-
-//widths per stream
-parameter STRM0_WIDTH = 32;
-parameter STRM1_WIDTH = 32;
-parameter STRM2_WIDTH = 32;
-parameter STRM3_WIDTH = 32;
-parameter STRM4_WIDTH = 1;
-parameter STRM5_WIDTH = 1;
-
-//depths per stream
-parameter STRM0_DEPTH = 2304;
-parameter STRM1_DEPTH = 2304;
-parameter STRM2_DEPTH = 2304;
-parameter STRM3_DEPTH = 2304;
-parameter STRM4_DEPTH = 1;
-parameter STRM5_DEPTH = 1;
-
-//offsets for each stream
-parameter STRM0_OFFSET = 0;
-parameter STRM1_OFFSET = 2304;
-parameter STRM2_OFFSET = 4608;
-parameter STRM3_OFFSET = 6912;
-parameter STRM4_OFFSET = 0;
-parameter STRM5_OFFSET = 0;
-
-
-reg clk;
-reg rst;
-
-reg [31:0] config_address = 0;
-reg config_ce = 0;
-reg config_we = 0;
-reg [31:0] config_d0 = 0;
-wire [31:0] config_q0;
-
-//multiple wire AXI Streams
-reg m_axis_0_afull;
-reg m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
-
-reg m_axis_1_afull;
-reg m_axis_1_tready;
-wire m_axis_1_tvalid;
-wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
-
-reg m_axis_2_afull;
-reg m_axis_2_tready;
-wire m_axis_2_tvalid;
-wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
-
-reg m_axis_3_afull;
-reg m_axis_3_tready;
-wire m_axis_3_tvalid;
-wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
-
-reg m_axis_4_afull;
-reg m_axis_4_tready;
-wire m_axis_4_tvalid;
-wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
-
-reg m_axis_5_afull;
-reg m_axis_5_tready;
-wire m_axis_5_tvalid;
-wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
-
-reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
-integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
-integer done = 0;
-reg [5:0] rng;
-
-//clock
-initial begin
- clk = 0;
- forever #5 clk = ~clk;
-end
-
-initial begin
- rst = 1;
- config_ce = 0;
- m_axis_0_afull = 0;
- m_axis_1_afull = 0;
- m_axis_2_afull = 0;
- m_axis_3_afull = 0;
- m_axis_4_afull = 0;
- m_axis_5_afull = 0;
- m_axis_0_tready = 1;
- m_axis_1_tready = 1;
- m_axis_2_tready = 1;
- m_axis_3_tready = 1;
- m_axis_4_tready = 1;
- m_axis_5_tready = 1;
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- fork
- begin
- $display("Starting to generate random AFULL");
- while(~done) begin
- rng = $random;
- m_axis_0_afull = rng[0];
- m_axis_1_afull = rng[1];
- m_axis_2_afull = rng[2];
- m_axis_3_afull = rng[3];
- m_axis_4_afull = rng[4];
- m_axis_5_afull = rng[5];
- @(negedge clk);
- end
- end
- join
-end
-
-
-//DUT
-memstream
-#(
- CONFIG_EN,
- NSTREAMS,
- MEM_DEPTH,
- MEM_WIDTH,
- MEM_INIT,
-
- //widths per stream
- STRM0_WIDTH,
- STRM1_WIDTH,
- STRM2_WIDTH,
- STRM3_WIDTH,
- STRM4_WIDTH,
- STRM5_WIDTH,
-
- //depths per stream
- STRM0_DEPTH,
- STRM1_DEPTH,
- STRM2_DEPTH,
- STRM3_DEPTH,
- STRM4_DEPTH,
- STRM5_DEPTH,
-
- //offsets for each stream
- STRM0_OFFSET,
- STRM1_OFFSET,
- STRM2_OFFSET,
- STRM3_OFFSET,
- STRM4_OFFSET,
- STRM5_OFFSET
-)
-dut
-(
- clk,
- ~rst,
-
- //optional AXI-Lite interface
- config_address,
- config_ce,
- config_we,
- config_d0,
- config_q0,
-
- //multiple output AXI Streams
- m_axis_0_afull,
- m_axis_0_tready,
- m_axis_0_tvalid,
- m_axis_0_tdata,
-
- m_axis_1_afull,
- m_axis_1_tready,
- m_axis_1_tvalid,
- m_axis_1_tdata,
-
- m_axis_2_afull,
- m_axis_2_tready,
- m_axis_2_tvalid,
- m_axis_2_tdata,
-
- m_axis_3_afull,
- m_axis_3_tready,
- m_axis_3_tvalid,
- m_axis_3_tdata,
-
- m_axis_4_afull,
- m_axis_4_tready,
- m_axis_4_tvalid,
- m_axis_4_tdata,
-
- m_axis_5_afull,
- m_axis_5_tready,
- m_axis_5_tvalid,
- m_axis_5_tdata
-
-
-);
-
-//stream checkers
-initial begin
- ptr0 = STRM0_OFFSET;
- ptr1 = STRM1_OFFSET;
- ptr2 = STRM2_OFFSET;
- ptr3 = STRM3_OFFSET;
- ptr4 = STRM4_OFFSET;
- ptr5 = STRM5_OFFSET;
- fork
- //check stream 0
- begin
- $display("Starting stream 0 checker");
- while(~done & (NSTREAMS > 0)) begin
- @(negedge clk);
- if(m_axis_0_tvalid) begin
- if(m_axis_0_tdata != golden[ptr0]) begin
- $display("Mismatch on stream 0");
- $stop();
- end
- //increment pointer
- ptr0 = ptr0 + 1;
- //rewind pointer if it's reached end
- if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
- ptr0 = STRM0_OFFSET;
- end
- end
- end
- //check stream 1
- begin
- $display("Starting stream 1 checker");
- while(~done & (NSTREAMS > 1)) begin
- @(negedge clk);
- if(m_axis_1_tvalid) begin
- if(m_axis_1_tdata != golden[ptr1]) begin
- $display("Mismatch on stream 1");
- $stop();
- end
- //increment pointer
- ptr1 = ptr1 + 1;
- //rewind pointer if it's reached end
- if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
- ptr1 = STRM1_OFFSET;
- end
- end
- end
-
- //check stream 2
- begin
- $display("Starting stream 2 checker");
- while(~done & (NSTREAMS > 2)) begin
- @(negedge clk);
- if(m_axis_2_tvalid) begin
- if(m_axis_2_tdata != golden[ptr2]) begin
- $display("Mismatch on stream 2");
- $stop();
- end
- //increment pointer
- ptr2 = ptr2 + 1;
- //rewind pointer if it's reached end
- if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
- ptr2 = STRM2_OFFSET;
- end
- end
- end
- //check stream 3
- begin
- $display("Starting stream 3 checker");
- while(~done & (NSTREAMS > 3)) begin
- @(negedge clk);
- if(m_axis_3_tvalid) begin
- if(m_axis_3_tdata != golden[ptr3]) begin
- $display("Mismatch on stream 3");
- $stop();
- end
- //increment pointer
- ptr3 = ptr3 + 1;
- //rewind pointer if it's reached end
- if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
- ptr3 = STRM3_OFFSET;
- end
- end
- end
- //check stream 4
- begin
- $display("Starting stream 4 checker");
- while(~done & (NSTREAMS > 4)) begin
- @(negedge clk);
- if(m_axis_4_tvalid) begin
- if(m_axis_4_tdata != golden[ptr4]) begin
- $display("Mismatch on stream 4");
- $stop();
- end
- //increment pointer
- ptr4 = ptr4 + 1;
- //rewind pointer if it's reached end
- if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
- ptr4 = STRM4_OFFSET;
- end
- end
- end
- //check stream 5
- begin
- $display("Starting stream 5 checker");
- while(~done & (NSTREAMS > 5)) begin
- @(negedge clk);
- if(m_axis_5_tvalid) begin
- if(m_axis_5_tdata != golden[ptr5]) begin
- $display("Mismatch on stream 5");
- $stop();
- end
- //increment pointer
- ptr5 = ptr5 + 1;
- //rewind pointer if it's reached end
- if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
- ptr5 = STRM5_OFFSET;
- end
- end
- end
- join
-end
-
-initial begin
- done = 0;
- $readmemh(MEM_CHECK,golden);
-// $dumpfile("wave.vcd");
-// $dumpvars(0,tb_memstream);
- @(negedge rst);
- #10000000
- $display("Test done!");
- done = 1;
- #1000
- $finish();
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/tb_memstream_writes.v b/finn-rtllib/memstream/sim/tb_memstream_writes.v
deleted file mode 100644
index c66807454b9a7f8ff7ab7008a504938740fb03a0..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/tb_memstream_writes.v
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`timescale 1ns/10ps
-
-module tb_memstream_writes;
-
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
-parameter CONFIG_EN = 1;
-parameter NSTREAMS = 2;//1 up to 6
-
-parameter MEM_DEPTH = 40;
-parameter MEM_WIDTH = 70;
-
-//widths per stream
-parameter STRM0_WIDTH = 70;
-parameter STRM1_WIDTH = 32;
-parameter STRM2_WIDTH = 32;
-parameter STRM3_WIDTH = 32;
-parameter STRM4_WIDTH = 1;
-parameter STRM5_WIDTH = 1;
-
-//depths per stream
-parameter STRM0_DEPTH = 20;
-parameter STRM1_DEPTH = 20;
-parameter STRM2_DEPTH = 2304;
-parameter STRM3_DEPTH = 2304;
-parameter STRM4_DEPTH = 1;
-parameter STRM5_DEPTH = 1;
-
-//offsets for each stream
-parameter STRM0_OFFSET = 0;
-parameter STRM1_OFFSET = 20;
-parameter STRM2_OFFSET = 4608;
-parameter STRM3_OFFSET = 6912;
-parameter STRM4_OFFSET = 0;
-parameter STRM5_OFFSET = 0;
-
-
-reg clk;
-reg rst;
-
-wire awready;
-reg awvalid;
-reg [31:0] awaddr;
-reg [2:0] awprot;
-//write data
-wire wready;
-reg wvalid;
-reg [31:0] wdata;
-reg [3:0] wstrb;
-//burst response
-reg bready;
-wire bvalid;
-wire [1:0] bresp;
-
-//Read channels
-//read address
-wire arready;
-reg arvalid;
-reg [31:0] araddr;
-reg [2:0] arprot;
-//read data
-reg rready;
-wire rvalid;
-wire [1:0] rresp;
-wire [31:0] rdata;
-
-//multiple wire AXI Streams
-reg m_axis_0_afull;
-reg m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
-
-reg m_axis_1_afull;
-reg m_axis_1_tready;
-wire m_axis_1_tvalid;
-wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
-
-reg m_axis_2_afull;
-reg m_axis_2_tready;
-wire m_axis_2_tvalid;
-wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
-
-reg m_axis_3_afull;
-reg m_axis_3_tready;
-wire m_axis_3_tvalid;
-wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
-
-reg m_axis_4_afull;
-reg m_axis_4_tready;
-wire m_axis_4_tvalid;
-wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
-
-reg m_axis_5_afull;
-reg m_axis_5_tready;
-wire m_axis_5_tvalid;
-wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
-
-reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
-reg [MEM_WIDTH-1:0] gword;
-integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
-integer done = 0;
-integer i, j;
-reg [5:0] rng;
-
-parameter NFOLDS_PER_WORD = (MEM_WIDTH+31)/32;
-
-task axi_write;
- input [MEM_WIDTH-1:0] data;
- input [31:0] adr;
- begin
- for(j=0; j<(1<<$clog2(NFOLDS_PER_WORD)); j=j+1) begin
- @(negedge clk);
- awvalid = 1;
- wvalid = 1;
- wdata = data>>(j*32);
- awaddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
- fork
- begin
- @(posedge awready);
- @(posedge clk) awvalid = 0;
- end
- begin
- @(posedge wready);
- @(posedge clk) wvalid = 0;
- end
- join
- @(posedge clk);
- end
- end
-endtask
-
-task axi_read;
- input [31:0] adr;
- output [MEM_WIDTH-1:0] data;
- begin
- data = 0;
- for(j=0; j<NFOLDS_PER_WORD; j=j+1) begin
- @(negedge clk);
- arvalid = 1;
- araddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
- rready = 1;
- fork
- begin
- @(posedge arready);
- @(posedge clk) arvalid = 0;
- end
- begin
- @(posedge rvalid);
- @(posedge clk) rready = 0;
- data = data | (rdata<<(32*j));
- end
- join
- @(posedge clk);
- end
- end
-endtask
-
-//clock
-initial begin
- clk = 0;
- forever #5 clk = ~clk;
-end
-
-initial begin
- rst = 1;
- awvalid = 0;
- arvalid = 0;
- wvalid = 0;
- rready = 1;
- bready = 1;
- m_axis_0_afull = 1;
- m_axis_1_afull = 1;
- m_axis_2_afull = 1;
- m_axis_3_afull = 1;
- m_axis_4_afull = 1;
- m_axis_5_afull = 1;
- m_axis_0_tready = 0;
- m_axis_1_tready = 0;
- m_axis_2_tready = 0;
- m_axis_3_tready = 0;
- m_axis_4_tready = 0;
- m_axis_5_tready = 0;
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- //random initialization of golden data
- for(i=0; i<MEM_DEPTH; i=i+1) begin
- gword = 0;
- repeat(NFOLDS_PER_WORD)
- gword = (gword << 32) | $random;
- golden[i] = gword;
- axi_write(golden[i],i);
- axi_read(i,gword);
- end
- //re-reset
- repeat(100) @(negedge clk);
- rst = 1;
- #100
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- @(negedge clk);
- //start reads
- m_axis_0_afull = 0;
- m_axis_1_afull = 0;
- m_axis_2_afull = 0;
- m_axis_3_afull = 0;
- m_axis_4_afull = 0;
- m_axis_5_afull = 0;
- m_axis_0_tready = 1;
- m_axis_1_tready = 1;
- m_axis_2_tready = 1;
- m_axis_3_tready = 1;
- m_axis_4_tready = 1;
- m_axis_5_tready = 1;
- fork
- begin
- $display("Starting to generate random AFULL");
- while(~done) begin
- rng = $random;
- m_axis_0_afull = rng[0];
- m_axis_1_afull = rng[1];
- m_axis_2_afull = rng[2];
- m_axis_3_afull = rng[3];
- m_axis_4_afull = rng[4];
- m_axis_5_afull = rng[5];
- @(negedge clk);
- end
- end
- join
-end
-
-
-//DUT
-memstream
-#(
- CONFIG_EN,
- NSTREAMS,
- MEM_DEPTH,
- MEM_WIDTH,
- ".",
- "auto",
- //widths per stream
- STRM0_WIDTH,
- STRM1_WIDTH,
- STRM2_WIDTH,
- STRM3_WIDTH,
- STRM4_WIDTH,
- STRM5_WIDTH,
- //depths per stream
- STRM0_DEPTH,
- STRM1_DEPTH,
- STRM2_DEPTH,
- STRM3_DEPTH,
- STRM4_DEPTH,
- STRM5_DEPTH,
- //offsets for each stream
- STRM0_OFFSET,
- STRM1_OFFSET,
- STRM2_OFFSET,
- STRM3_OFFSET,
- STRM4_OFFSET,
- STRM5_OFFSET
-)
-dut
-(
- clk,
- ~rst,
-
- //optional AXI-Lite interface
- awready,
- awvalid,
- awaddr,
- awprot,
- //write data
- wready,
- wvalid,
- wdata,
- wstrb,
- //burst response
- bready,
- bvalid,
- bresp,
-
- //Read channels
- //read address
- arready,
- arvalid,
- araddr,
- arprot,
- //read data
- rready,
- rvalid,
- rresp,
- rdata,
-
- //multiple output AXI Streams
- m_axis_0_afull,
- m_axis_0_tready,
- m_axis_0_tvalid,
- m_axis_0_tdata,
- m_axis_1_afull,
- m_axis_1_tready,
- m_axis_1_tvalid,
- m_axis_1_tdata,
- m_axis_2_afull,
- m_axis_2_tready,
- m_axis_2_tvalid,
- m_axis_2_tdata,
- m_axis_3_afull,
- m_axis_3_tready,
- m_axis_3_tvalid,
- m_axis_3_tdata,
- m_axis_4_afull,
- m_axis_4_tready,
- m_axis_4_tvalid,
- m_axis_4_tdata,
- m_axis_5_afull,
- m_axis_5_tready,
- m_axis_5_tvalid,
- m_axis_5_tdata
-
-);
-
-//stream checkers
-initial begin
- ptr0 = STRM0_OFFSET;
- ptr1 = STRM1_OFFSET;
- ptr2 = STRM2_OFFSET;
- ptr3 = STRM3_OFFSET;
- ptr4 = STRM4_OFFSET;
- ptr5 = STRM5_OFFSET;
- fork
- //check stream 0
- begin
- $display("Starting stream 0 checker");
- while(~done & (NSTREAMS > 0)) begin
- @(negedge clk);
- if(m_axis_0_tvalid & m_axis_0_tready) begin
- if(m_axis_0_tdata != golden[ptr0]) begin
- $display("Mismatch on stream 0");
- $stop();
- end
- //increment pointer
- ptr0 = ptr0 + 1;
- //rewind pointer if it's reached end
- if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
- ptr0 = STRM0_OFFSET;
- end
- end
- end
- //check stream 1
- begin
- $display("Starting stream 1 checker");
- while(~done & (NSTREAMS > 1)) begin
- @(negedge clk);
- if(m_axis_1_tvalid & m_axis_1_tready) begin
- if(m_axis_1_tdata != golden[ptr1]) begin
- $display("Mismatch on stream 1");
- $stop();
- end
- //increment pointer
- ptr1 = ptr1 + 1;
- //rewind pointer if it's reached end
- if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
- ptr1 = STRM1_OFFSET;
- end
- end
- end
- //check stream 2
- begin
- $display("Starting stream 2 checker");
- while(~done & (NSTREAMS > 2)) begin
- @(negedge clk);
- if(m_axis_2_tvalid & m_axis_2_tready) begin
- if(m_axis_2_tdata != golden[ptr2]) begin
- $display("Mismatch on stream 2");
- $stop();
- end
- //increment pointer
- ptr2 = ptr2 + 1;
- //rewind pointer if it's reached end
- if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
- ptr2 = STRM2_OFFSET;
- end
- end
- end
- //check stream 3
- begin
- $display("Starting stream 3 checker");
- while(~done & (NSTREAMS > 3)) begin
- @(negedge clk);
- if(m_axis_3_tvalid & m_axis_3_tready) begin
- if(m_axis_3_tdata != golden[ptr3]) begin
- $display("Mismatch on stream 3");
- $stop();
- end
- //increment pointer
- ptr3 = ptr3 + 1;
- //rewind pointer if it's reached end
- if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
- ptr3 = STRM3_OFFSET;
- end
- end
- end
- //check stream 4
- begin
- $display("Starting stream 4 checker");
- while(~done & (NSTREAMS > 4)) begin
- @(negedge clk);
- if(m_axis_4_tvalid & m_axis_4_tready) begin
- if(m_axis_4_tdata != golden[ptr4]) begin
- $display("Mismatch on stream 4");
- $stop();
- end
- //increment pointer
- ptr4 = ptr4 + 1;
- //rewind pointer if it's reached end
- if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
- ptr4 = STRM4_OFFSET;
- end
- end
- end
- //check stream 5
- begin
- $display("Starting stream 5 checker");
- while(~done & (NSTREAMS > 5)) begin
- @(negedge clk);
- if(m_axis_5_tvalid & m_axis_5_tready) begin
- if(m_axis_5_tdata != golden[ptr5]) begin
- $display("Mismatch on stream 5");
- $stop();
- end
- //increment pointer
- ptr5 = ptr5 + 1;
- //rewind pointer if it's reached end
- if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
- ptr5 = STRM5_OFFSET;
- end
- end
- end
- join
-end
-
-initial begin
- done = 0;
- @(negedge rst);
- $dumpfile("wave.vcd");
- $dumpvars(0,tb_memstream_writes);
- #50000
- $display("Test done!");
- done = 1;
- #1000
- $finish();
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh
deleted file mode 100755
index 7cb0497d261ac41a763bad8e58afabb204887d39..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/test.sh
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-iverilog ../hdl/*.v tb_memstream_writes.v -o sim
-./sim
diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
index 87565bc5613ce783d6a8067e8323d2358adb8061..4ad14af637abab8ec288ebd97c3480ba9001b6c9 100644
--- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
+++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
@@ -1,98 +1,31 @@
-
-# Loading additional proc with user specified bodies to compute parameter values.
-source [file join [file dirname [file dirname [info script]]] gui/memstream_v1_0.gtcl]
-
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
- ipgui::add_param $IPINST -name "AXILITE_ADDR_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0}
- ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} -widget comboBox
- ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_WIDTH" -parent ${Page_0}
-
+ ipgui::add_param $IPINST -name "DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0}
-}
-
-proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change
- set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH}
- set MEM_DEPTH ${PARAM_VALUE.MEM_DEPTH}
- set MEM_WIDTH ${PARAM_VALUE.MEM_WIDTH}
- set values(MEM_DEPTH) [get_property value $MEM_DEPTH]
- set values(MEM_WIDTH) [get_property value $MEM_WIDTH]
- set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(MEM_DEPTH) $values(MEM_WIDTH)] $AXILITE_ADDR_WIDTH
-}
-
-proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH } {
- # Procedure called to validate AXILITE_ADDR_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
- # Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
- # Procedure called to validate CONFIG_EN
- return true
-}
-
-proc update_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
- # Procedure called to update MEM_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
- # Procedure called to validate MEM_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
- # Procedure called to update MEM_INIT when any of the dependent parameters in the arguments change
-}
-proc validate_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
- # Procedure called to validate MEM_INIT
- return true
}
-proc update_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to update MEM_WIDTH when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+ # Procedure called to update DEPTH when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to validate MEM_WIDTH
+proc validate_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+ # Procedure called to validate DEPTH
return true
}
-proc update_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
- # Procedure called to update NSTREAMS when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+ # Procedure called to update INIT_FILE when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
- # Procedure called to validate NSTREAMS
+proc validate_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+ # Procedure called to validate INIT_FILE
return true
}
@@ -105,192 +38,29 @@ proc validate_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } {
return true
}
-proc update_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to update STRM0_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to validate STRM0_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to update STRM0_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to validate STRM0_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to update STRM0_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to validate STRM0_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to update STRM1_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to validate STRM1_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to update STRM1_OFFSET when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+ # Procedure called to update WIDTH when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to validate STRM1_OFFSET
+proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+ # Procedure called to validate WIDTH
return true
}
-proc update_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to update STRM1_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to validate STRM1_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to update STRM2_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to validate STRM2_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to update STRM2_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to validate STRM2_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to update STRM2_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to validate STRM2_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to update STRM3_DEPTH when any of the dependent parameters in the arguments change
-}
-proc validate_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to validate STRM3_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to update STRM3_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to validate STRM3_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to update STRM3_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to validate STRM3_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to update STRM4_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to validate STRM4_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to update STRM4_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to validate STRM4_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to update STRM4_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to validate STRM4_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to update STRM5_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to validate STRM5_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to update STRM5_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to validate STRM5_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to update STRM5_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to validate STRM5_WIDTH
- return true
-}
-
-
-proc update_MODELPARAM_VALUE.CONFIG_EN { MODELPARAM_VALUE.CONFIG_EN PARAM_VALUE.CONFIG_EN } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.CONFIG_EN}] ${MODELPARAM_VALUE.CONFIG_EN}
-}
-
-proc update_MODELPARAM_VALUE.NSTREAMS { MODELPARAM_VALUE.NSTREAMS PARAM_VALUE.NSTREAMS } {
+proc update_MODELPARAM_VALUE.DEPTH { MODELPARAM_VALUE.DEPTH PARAM_VALUE.DEPTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.NSTREAMS}] ${MODELPARAM_VALUE.NSTREAMS}
+ set_property value [get_property value ${PARAM_VALUE.DEPTH}] ${MODELPARAM_VALUE.DEPTH}
}
-proc update_MODELPARAM_VALUE.MEM_DEPTH { MODELPARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_DEPTH } {
+proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_DEPTH}] ${MODELPARAM_VALUE.MEM_DEPTH}
+ set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH}
}
-proc update_MODELPARAM_VALUE.MEM_WIDTH { MODELPARAM_VALUE.MEM_WIDTH PARAM_VALUE.MEM_WIDTH } {
+proc update_MODELPARAM_VALUE.INIT_FILE { MODELPARAM_VALUE.INIT_FILE PARAM_VALUE.INIT_FILE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_WIDTH}] ${MODELPARAM_VALUE.MEM_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.MEM_INIT { MODELPARAM_VALUE.MEM_INIT PARAM_VALUE.MEM_INIT } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_INIT}] ${MODELPARAM_VALUE.MEM_INIT}
+ set_property value [get_property value ${PARAM_VALUE.INIT_FILE}] ${MODELPARAM_VALUE.INIT_FILE}
}
proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.RAM_STYLE } {
@@ -298,97 +68,8 @@ proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.
set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE}
}
-proc update_MODELPARAM_VALUE.STRM0_WIDTH { MODELPARAM_VALUE.STRM0_WIDTH PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_WIDTH}] ${MODELPARAM_VALUE.STRM0_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_WIDTH { MODELPARAM_VALUE.STRM1_WIDTH PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_WIDTH}] ${MODELPARAM_VALUE.STRM1_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_WIDTH { MODELPARAM_VALUE.STRM2_WIDTH PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_WIDTH}] ${MODELPARAM_VALUE.STRM2_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_WIDTH { MODELPARAM_VALUE.STRM3_WIDTH PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_WIDTH}] ${MODELPARAM_VALUE.STRM3_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_WIDTH { MODELPARAM_VALUE.STRM4_WIDTH PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_WIDTH}] ${MODELPARAM_VALUE.STRM4_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_WIDTH { MODELPARAM_VALUE.STRM5_WIDTH PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_WIDTH}] ${MODELPARAM_VALUE.STRM5_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM0_DEPTH { MODELPARAM_VALUE.STRM0_DEPTH PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_DEPTH}] ${MODELPARAM_VALUE.STRM0_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_DEPTH { MODELPARAM_VALUE.STRM1_DEPTH PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_DEPTH}] ${MODELPARAM_VALUE.STRM1_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_DEPTH { MODELPARAM_VALUE.STRM2_DEPTH PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_DEPTH}] ${MODELPARAM_VALUE.STRM2_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_DEPTH { MODELPARAM_VALUE.STRM3_DEPTH PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_DEPTH}] ${MODELPARAM_VALUE.STRM3_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_DEPTH { MODELPARAM_VALUE.STRM4_DEPTH PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_DEPTH}] ${MODELPARAM_VALUE.STRM4_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_DEPTH { MODELPARAM_VALUE.STRM5_DEPTH PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_DEPTH}] ${MODELPARAM_VALUE.STRM5_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM0_OFFSET { MODELPARAM_VALUE.STRM0_OFFSET PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_OFFSET}] ${MODELPARAM_VALUE.STRM0_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_OFFSET { MODELPARAM_VALUE.STRM1_OFFSET PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_OFFSET}] ${MODELPARAM_VALUE.STRM1_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_OFFSET { MODELPARAM_VALUE.STRM2_OFFSET PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_OFFSET}] ${MODELPARAM_VALUE.STRM2_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_OFFSET { MODELPARAM_VALUE.STRM3_OFFSET PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_OFFSET}] ${MODELPARAM_VALUE.STRM3_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_OFFSET { MODELPARAM_VALUE.STRM4_OFFSET PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_OFFSET}] ${MODELPARAM_VALUE.STRM4_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.AXILITE_ADDR_WIDTH } {
+proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH}
+ # WARNING: There is no corresponding user parameter named "AXILITE_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 11 ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH}
}
diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
index cde66f1ae2cf633ef97ed2715543cfe12253d510..7791647abf1c5a51c0425ae835471ec9ceb7c21c 100644
--- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
+++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
@@ -39,8 +39,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for channelwise ops:
# input 0 is the input tensor, shape (..., NumChannels)
# input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel)
@@ -87,7 +85,6 @@ class ChannelwiseOp_Batch(HLSCustomOp):
def __init__(self, onnx_node, **kwargs):
super().__init__(onnx_node, **kwargs)
- self.decoupled_wrapper = templates.decoupled_wrapper
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
index aa987384ddf80bd13d417a762c0291f5917b39bf..fd41e1f9ad1431790b66be728b78540a910947cd 100644
--- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
@@ -46,8 +46,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for MatrixVectorActivation:
# input 0 is the input tensor, shape (.., i_size) = (..., MW)
# input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH)
@@ -62,7 +60,6 @@ class MatrixVectorActivation(HLSCustomOp):
def __init__(self, onnx_node, **kwargs):
super().__init__(onnx_node, **kwargs)
- self.decoupled_wrapper = templates.decoupled_wrapper
def get_nodeattr_types(self):
my_attrs = {
@@ -867,28 +864,10 @@ class MatrixVectorActivation(HLSCustomOp):
self.make_weight_file(weights, "decoupled_npy", weight_filename_sim)
if mem_mode == "decoupled":
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(
- code_gen_dir
- )
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- weights, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_weights = np.zeros_like(weights, dtype=np.float32)
- else:
- synth_weights = weights
- self.make_weight_file(
- synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth
+ weights, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception(
@@ -1379,7 +1358,7 @@ class MatrixVectorActivation(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:FINN:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -1387,22 +1366,16 @@ class MatrixVectorActivation(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_wmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_wmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -1413,11 +1386,11 @@ class MatrixVectorActivation(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(
diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py
index c7bbc3f139b64f57943b2b099083a9611951e9c4..4e03e6daf9aee9aee2318ac1bc840b6387a40ccd 100644
--- a/src/finn/custom_op/fpgadataflow/templates.py
+++ b/src/finn/custom_op/fpgadataflow/templates.py
@@ -109,107 +109,6 @@ export_design -format ip_catalog
exit 0
"""
-# verilog wrapper for decoupled mem mode
-decoupled_wrapper = """
-module $TOPNAME$(
-ap_clk,
-ap_rst_n,
-in0_$HLS_SNAME$_TDATA,
-in0_$HLS_SNAME$_TVALID,
-in0_$HLS_SNAME$_TREADY,
-out_$HLS_SNAME$_TDATA,
-out_$HLS_SNAME$_TVALID,
-out_$HLS_SNAME$_TREADY
-);
-
-input ap_clk;
-input ap_rst_n;
-input $IN_RANGE$ in0_$HLS_SNAME$_TDATA;
-input in0_$HLS_SNAME$_TVALID;
-output in0_$HLS_SNAME$_TREADY;
-output $OUT_RANGE$ out_$HLS_SNAME$_TDATA;
-output out_$HLS_SNAME$_TVALID;
-input out_$HLS_SNAME$_TREADY;
-
-reg [31:0] config_address = 0;
-reg config_ce = 0;
-reg config_we = 0;
-reg [31:0] config_d0 = 0;
-wire [31:0] config_q0;
-
-//multiple wire AXI Streams
-wire m_axis_0_afull;
-// FIFO count to generate programmable full
-wire [5:0] fifo_0_count;
-wire m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire $WEIGHT_RANGE$ m_axis_0_tdata;
-
-//memstream component
-
-memstream
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for
-// memory, set per-stream offsets in memory, set per-stream widths
-.CONFIG_EN(1),
-.NSTREAMS(1),
-.MEM_DEPTH($MEM_DEPTH$),
-.MEM_WIDTH($WEIGHT_WIDTH$),
-.MEM_INIT("./"),
-.RAM_STYLE("$RAM_STYLE$"),
-
-//widths per stream
-.STRM0_WIDTH($WEIGHT_WIDTH$),
-
-//depths per stream
-.STRM0_DEPTH($WSTREAM_DEPTH$),
-
-//offsets for each stream
-.STRM0_OFFSET(0)
-)
-mem
-(
-.aclk(ap_clk),
-.aresetn(ap_rst_n),
-
-//optional configuration interface compatible with ap_memory
-.config_address(config_address),
-.config_ce(config_ce),
-.config_we(config_we),
-.config_d0(config_d0),
-.config_q0(config_q0),
-
-//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
-.m_axis_0_afull(m_axis_0_afull),
-.m_axis_0_tready(m_axis_0_tready),
-.m_axis_0_tvalid(m_axis_0_tvalid),
-.m_axis_0_tdata(m_axis_0_tdata)
-
-
-);
-
-
-//MVA_Stream_Unit
-
-$LAYER_NAME$
-MVA_Stream_U
-(
-.ap_clk(ap_clk), //input
-.ap_rst_n(ap_rst_n), //input
-.in0_$HLS_SNAME$_TDATA(in0_$HLS_SNAME$_TDATA), //$IN_RANGE$ input
-.in0_$HLS_SNAME$_TVALID(in0_$HLS_SNAME$_TVALID), //input
-.in0_$HLS_SNAME$_TREADY(in0_$HLS_SNAME$_TREADY), //output
-.weights_$HLS_SNAME$_TDATA(m_axis_0_tdata), //$WEIGHT_RANGE$ input
-.weights_$HLS_SNAME$_TVALID(m_axis_0_tvalid), //input
-.weights_$HLS_SNAME$_TREADY(m_axis_0_tready), //output
-.out_$HLS_SNAME$_TDATA(out_$HLS_SNAME$_TDATA), //$OUT_RANGE$ output
-.out_$HLS_SNAME$_TVALID(out_$HLS_SNAME$_TVALID), //output
-.out_$HLS_SNAME$_TREADY(out_$HLS_SNAME$_TREADY) //input
-);
-
-endmodule
-"""
-
ip_package_tcl = """
## IP Info
set Vendor "xilinx.com"
diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py
index 292f70941a3c18a594d904eb4922dc4bce550d82..eab50c2cbc309afa446451a8cedfb4689f280a77 100644
--- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py
+++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py
@@ -45,8 +45,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for Thresholding:
# input 0 is the input tensor, shape (..., NumChannels)
# input 1 is the threshold tensor, shape (NumChannels, n_thres)
@@ -59,7 +57,6 @@ class Thresholding_Batch(HLSCustomOp):
def __init__(self, onnx_node, **kwargs):
super().__init__(onnx_node, **kwargs)
- self.decoupled_wrapper = templates.decoupled_wrapper
def get_nodeattr_types(self):
my_attrs = {
@@ -457,26 +454,10 @@ class Thresholding_Batch(HLSCustomOp):
weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir)
self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim)
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(code_gen_dir)
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- thresholds, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_thresholds = np.zeros_like(thresholds, dtype=np.float32)
- else:
- synth_thresholds = thresholds
- self.make_weight_file(
- synth_thresholds, "decoupled_verilog_dat", weight_filename_rtl_synth
+ thresholds, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception("Unrecognized mem_mode")
@@ -843,7 +824,7 @@ class Thresholding_Batch(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:FINN:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -851,22 +832,16 @@ class Thresholding_Batch(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_tmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_tmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -877,11 +852,11 @@ class Thresholding_Batch(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(
diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
index da79933f26b27d3b84946cacad7a9ededb16003c..a7aaa186dff0a589d5c0a3a199577c789ea0bb6c 100644
--- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
@@ -580,28 +580,10 @@ class VectorVectorActivation(HLSCustomOp):
self.make_weight_file(weights, "decoupled_npy", weight_filename_sim)
if mem_mode == "decoupled":
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(
- code_gen_dir
- )
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
- self.make_weight_file(
- weights, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_weights = np.zeros_like(weights, dtype=np.float32)
- else:
- synth_weights = weights
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth
+ weights, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception(
@@ -1068,7 +1050,7 @@ class VectorVectorActivation(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:FINN:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -1076,22 +1058,16 @@ class VectorVectorActivation(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_wmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_wmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -1102,11 +1078,11 @@ class VectorVectorActivation(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(