From 53ffa3438dc130e71c46f7db2730095daba04204 Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Tue, 5 Jul 2022 16:15:35 +0200
Subject: [PATCH] Adapt to upcoming FINN release
---
finn-rtllib/swg/swg_template_wrapper.v | 36 +++++++++----------
.../convolutioninputgenerator_rtl.py | 12 +++----
...est_fpgadataflow_convinputgenerator_rtl.py | 12 +++----
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/finn-rtllib/swg/swg_template_wrapper.v b/finn-rtllib/swg/swg_template_wrapper.v
index db0556d94..510418453 100644
--- a/finn-rtllib/swg/swg_template_wrapper.v
+++ b/finn-rtllib/swg/swg_template_wrapper.v
@@ -3,12 +3,12 @@
module $TOP_MODULE_NAME$ (
ap_clk,
ap_rst_n,
- in0_V_V_TDATA,
- in0_V_V_TVALID,
- in0_V_V_TREADY,
- out_V_V_TDATA,
- out_V_V_TVALID,
- out_V_V_TREADY
+ in0_V_TDATA,
+ in0_V_TVALID,
+ in0_V_TREADY,
+ out_V_TDATA,
+ out_V_TVALID,
+ out_V_TREADY
);
parameter BIT_WIDTH = $BIT_WIDTH$;
@@ -21,13 +21,13 @@ parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT;
input ap_clk;
input ap_rst_n;
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000.000000" *) //todo: make configurable or set later
-input [BUF_IN_WIDTH-1:0] in0_V_V_TDATA;
-input in0_V_V_TVALID;
-output in0_V_V_TREADY;
+input [BUF_IN_WIDTH-1:0] in0_V_TDATA;
+input in0_V_TVALID;
+output in0_V_TREADY;
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000.000000" *)
-output [BUF_OUT_WIDTH-1:0] out_V_V_TDATA;
-output out_V_V_TVALID;
-input out_V_V_TREADY;
+output [BUF_OUT_WIDTH-1:0] out_V_TDATA;
+output out_V_TVALID;
+input out_V_TREADY;
$TOP_MODULE_NAME$_impl
#()
@@ -35,12 +35,12 @@ impl
(
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
- .in0_V_V_TDATA(in0_V_V_TDATA),
- .in0_V_V_TVALID(in0_V_V_TVALID),
- .in0_V_V_TREADY(in0_V_V_TREADY),
- .out_V_V_TDATA(out_V_V_TDATA),
- .out_V_V_TVALID(out_V_V_TVALID),
- .out_V_V_TREADY(out_V_V_TREADY)
+ .in0_V_V_TDATA(in0_V_TDATA),
+ .in0_V_V_TVALID(in0_V_TVALID),
+ .in0_V_V_TREADY(in0_V_TREADY),
+ .out_V_V_TDATA(out_V_TDATA),
+ .out_V_V_TVALID(out_V_TVALID),
+ .out_V_V_TREADY(out_V_TREADY)
);
endmodule //TOP_MODULE_NAME
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
index af1896092..936954258 100755
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
@@ -31,11 +31,11 @@ from math import copysign
import numpy as np
import os
-from finn.core.datatype import DataType
+from qonnx.core.datatype import DataType
+from qonnx.custom_op.general import im2col
+from qonnx.custom_op.general.im2col import compute_conv_output_dim
from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp
-from finn.custom_op.general.im2col import compute_conv_output_dim
from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
-from finn.custom_op.general import im2col
from finn.util.basic import (
get_rtlsim_trace_depth,
@@ -625,7 +625,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dict["$ELEM_PER_WINDOW$"] = [str(elem_per_window)]
- with open("/workspace/finn/finn-rtllib/swg/swg_template_default.sv", "r") as f:
+ with open(os.environ['FINN_ROOT']+"/finn-rtllib/swg/swg_template_default.sv", "r") as f:
template = f.read()
##### END CODE GEN FOR DEFAULT STYLE #####
@@ -976,7 +976,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dict["$WRITE_CMD_MAP$"]=["{{ {}, {}, {}, {}, {}, {}, {} }}".format(
start_sequence[1][1],loop_sequence_1[1][1],loop_sequence_1[3][1],loop_sequence_2[1][1],loop_sequence_2[3][1],end_sequence[1][1],end_sequence[3][1])]
- with open("/workspace/finn/finn-rtllib/swg/swg_template_parallel.sv", "r") as f:
+ with open(os.environ['FINN_ROOT']+"/finn-rtllib/swg/swg_template_parallel.sv", "r") as f:
template = f.read()
##### END CODE GEN FOR PARALLEL STYLE #####
@@ -997,7 +997,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
else:
code_gen_dict["$RAM_STYLE$"]=["(* ram_style = \"{}\" *)".format(ram_style)]
- with open("/workspace/finn/finn-rtllib/swg/swg_template_wrapper.v", "r") as f:
+ with open(os.environ['FINN_ROOT']+"/finn-rtllib/swg/swg_template_wrapper.v", "r") as f:
template_wrapper = f.read()
for key in code_gen_dict:
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
index 01133dc5f..c0bf799fa 100755
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
@@ -33,15 +33,15 @@ from onnx import TensorProto, helper
import finn.core.onnx_exec as oxe
from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer
-from finn.core.datatype import DataType
-from finn.core.modelwrapper import ModelWrapper
-from finn.custom_op.general.im2col import compute_conv_output_dim
-from finn.custom_op.registry import getCustomOp
+from qonnx.core.datatype import DataType
+from qonnx.core.modelwrapper import ModelWrapper
+from qonnx.custom_op.general.im2col import compute_conv_output_dim
+from qonnx.custom_op.registry import getCustomOp
+from qonnx.transformation.general import GiveUniqueNodeNames
+from qonnx.util.basic import gen_finn_dt_tensor
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
-from finn.transformation.general import GiveUniqueNodeNames
-from finn.util.basic import gen_finn_dt_tensor
def make_single_im2col_modelwrapper(
k, ifm_ch, ifm_dim, ofm_dim, stride, dilation, idt
--
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