From 51983a191ac58e99a01f8bc3f99fee6ef60a97f8 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Wed, 6 Oct 2021 15:45:27 +0200
Subject: [PATCH] [Stitch] always enable user-resolve mode for bus interfaces
---
.../transformation/fpgadataflow/create_stitched_ip.py | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index c2ded29d2..327c7867f 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -332,12 +332,13 @@ class CreateStitchedIP(Transformation):
)
tcl.append("set_property core_revision 2 [ipx::find_open_core %s]" % block_vlnv)
tcl.append("ipx::create_xgui_files [ipx::find_open_core %s]" % block_vlnv)
+ # mark bus interface params as user-resolvable to avoid FREQ_MHZ mismatches
+ tcl.append(
+ "set_property value_resolve_type user [ipx::get_bus_parameters "
+ "-of [ipx::get_bus_interfaces -of [ipx::current_core ]]]"
+ )
# if targeting Vitis, add some properties to the IP
if self.vitis:
- tcl.append(
- "set_property value_resolve_type user [ipx::get_bus_parameters "
- "-of [ipx::get_bus_interfaces -of [ipx::current_core ]]]"
- )
# replace source code with dcp
tcl.append(
"set_property sdx_kernel true [ipx::find_open_core %s]" % block_vlnv
--
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