From 4c04af8da866d2dde88455bd920c6fc17b06493b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= <thomas.preusser@xilinx.com>
Date: Thu, 11 Aug 2022 06:14:48 +0100
Subject: [PATCH] Add IRQ signalling output for input bounds violation (to be
externalized).
---
src/finn/custom_op/fpgadataflow/lookup.py | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py
index d3c8af56e..6425edd56 100644
--- a/src/finn/custom_op/fpgadataflow/lookup.py
+++ b/src/finn/custom_op/fpgadataflow/lookup.py
@@ -259,8 +259,8 @@ class Lookup(HLSCustomOp):
]
elif mem_mode == "external":
self.code_gen_dict["$DOCOMPUTE$"] = [
- """StreamingLookup_ext<EmbeddingSize>
- (in0, out, mem, size, oob_count);"""
+ """StreamingLookup_ext<EmbeddingSize>(in0, out, mem, size, oob_count);
+ oob_irq = oob_count != 0;"""
]
def blackboxfunction(self):
@@ -279,7 +279,7 @@ class Lookup(HLSCustomOp):
"void "
+ self.onnx_node.name
+ "(hls::stream<T_SRC> &in0, hls::stream<T_DST> &out, "
- + "T_DST const *const mem, unsigned const size, unsigned &oob_count)"
+ + "T_DST const *const mem, unsigned const size, unsigned &oob_count, bool &oob_irq)"
]
def pragmas(self):
@@ -298,12 +298,9 @@ class Lookup(HLSCustomOp):
elif mem_mode == "external":
my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem")
my_pragmas.append("#pragma HLS INTERFACE s_axilite port=mem bundle=control")
- my_pragmas.append(
- "#pragma HLS INTERFACE s_axilite port=size bundle=control"
- )
- my_pragmas.append(
- "#pragma HLS INTERFACE s_axilite port=oob_count bundle=control"
- )
+ my_pragmas.append("#pragma HLS INTERFACE s_axilite port=size bundle=control")
+ my_pragmas.append("#pragma HLS INTERFACE s_axilite port=oob_count bundle=control")
+ my_pragmas.append("#pragma HLS INTERFACE ap_none port=oob_irq")
else:
raise Exception("Unrecognized mem_mode: " + mem_mode)
self.code_gen_dict["$PRAGMAS$"] = my_pragmas
@@ -474,4 +471,5 @@ class Lookup(HLSCustomOp):
if mem_mode == "external":
intf_names["axilite"] = ["s_axi_control"]
intf_names["aximm"] = [("m_axi_gmem", self.get_nodeattr("ext_mem_width"))]
+ intf_names["oob_irq"] = ["ap_none"]
return intf_names
--
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