From 49e02b15b1a50f6bfbfcb77a6cc61891b740092b Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Wed, 6 Oct 2021 15:44:09 +0200
Subject: [PATCH] [Zynq] fix auto fclk setting req mode for Zynq UltraScale+
---
src/finn/transformation/fpgadataflow/templates.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index ae13f6e4e..b881bf788 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -134,6 +134,7 @@ if {$ZYNQ_TYPE == "zynq_us+"} {
set_property -dict [list CONFIG.PSU__USE__S_AXI_GP2 {1}] [get_bd_cells zynq_ps]
set_property -dict [list CONFIG.PSU__USE__M_AXI_GP1 {0}] [get_bd_cells zynq_ps]
#set frequency of PS clock (this can't always be exactly met)
+ set_property -dict [list CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0}] [get_bd_cells zynq_ps]
set_property -dict [list CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ [expr int($FREQ_MHZ)]] [get_bd_cells zynq_ps]
} elseif {$ZYNQ_TYPE == "zynq_7000"} {
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 zynq_ps
--
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