From 485299e4a7a14099cff3b63ba6325d22836427e8 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Mon, 12 Oct 2020 23:02:39 +0200
Subject: [PATCH] [Transform] more flexible AXI lite name handling for renaming
---
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 3470e9525..069ceccbc 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -128,7 +128,8 @@ class CreateStitchedIP(Transformation):
"[get_bd_intf_pins %s/%s]" % (inst_name, axilite_intf_name[0])
)
self.connect_cmds.append(
- "set_property name s_axi_control " "[get_bd_intf_ports s_axi_control_0]"
+ "set_property name s_axi_control "
+ "[get_bd_intf_ports %s_0]" % axilite_intf_name[0]
)
assert (
self.has_axilite is False
--
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