diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py index c46e8ca6789755e5483ae9a6a42cb83dce9247bf..4546832cd46b829443bbdf87f867b628932ff1f2 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py @@ -2,7 +2,6 @@ import os import subprocess import tempfile as tmp -from finn.core.utils import get_by_name from finn.transformation import Transformation @@ -28,13 +27,22 @@ class MakePYNQProject(Transformation): raise Exception("Ensure the PYNQ-HelloWorld utility repo is cloned.") ipstitch_path = model.get_metadata_prop("vivado_stitch_proj") if ipstitch_path is None or (not os.path.isdir(ipstitch_path)): - raise Exception("No stitched IPI design found, apply CodeGen_ipstitch first.") + raise Exception( + "No stitched IPI design found, apply CodeGen_ipstitch first." + ) + vivado_stitch_vlnv = model.get_metadata_prop("vivado_stitch_vlnv") + if vivado_stitch_vlnv is None: + raise Exception( + "No vlnv for stitched IP found, apply CodeGen_ipstitch first." + ) # TODO extract the actual in-out bytes from graph in_bytes = 8 out_bytes = 8 - in_if_name = "in0_V_V" - out_if_name = "out_V_V" + in_if_name = "in0_V_V_0" + out_if_name = "out_V_V_0" + clk_name = "ap_clk_0" + nrst_name = "ap_rst_n_0" # create a temporary folder for the project vivado_pynq_proj_dir = tmp.mkdtemp(prefix="vivado_pynq_proj_") @@ -59,7 +67,7 @@ set config_ip_repo %s # non-path arguments # VLNV of the IP block -set config_ip_vlnv xilinx.com:hls:resize_accel:1.0 +set config_ip_vlnv %s # width of the AXI stream into the IP, in bytes set config_ip_bytes_in %d # width of the AXI stream out of the IP, in bytes @@ -68,16 +76,27 @@ set config_ip_bytes_out %d set config_ip_axis_name_in %s # the name of the output AXI stream interface set config_ip_axis_name_out %s +# the name of the clock signal +set config_ip_clk_name %s +# the name of the active-low reset signal +set config_ip_nrst_name %s # whether the IP needs an AXI Lite interface for control set config_ip_use_axilite 0 """ % ( - vivado_pynq_proj_dir, ipstitch_path + "/ip", in_bytes, out_bytes, - in_if_name, out_if_name + vivado_pynq_proj_dir, + ipstitch_path + "/ip", + vivado_stitch_vlnv, + in_bytes, + out_bytes, + in_if_name, + out_if_name, + clk_name, + nrst_name, ) with open(vivado_pynq_proj_dir + "/ip_config.tcl", "w") as f: f.write(ip_config_tcl) - # create a shell script and call Vivado + # create a shell script for project creation and synthesis make_project_sh = vivado_pynq_proj_dir + "/make_project.sh" working_dir = os.environ["PWD"] with open(make_project_sh, "w") as f: @@ -87,6 +106,16 @@ set config_ip_use_axilite 0 f.write("export ip_config=%s\n" % (vivado_pynq_proj_dir + "/ip_config.tcl")) f.write("make block_design\n") f.write("cd {}\n".format(working_dir)) + synth_project_sh = vivado_pynq_proj_dir + "/synth_project.sh" + with open(synth_project_sh, "w") as f: + f.write("#!/bin/bash \n") + f.write("cd {}\n".format(pynq_shell_path)) + f.write("export platform=%s\n" % (self.platform)) + f.write("export ip_config=%s\n" % (vivado_pynq_proj_dir + "/ip_config.tcl")) + f.write("make bitfile\n") + f.write("cd {}\n".format(working_dir)) + # call the project creation script + # synthesis script will be called with a separate transformation bash_command = ["bash", make_project_sh] process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) process_compile.communicate()