From 431d74c7fe2a2a96047180f1ccad777ffcee2f33 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Wed, 1 Feb 2023 18:13:21 +0000
Subject: [PATCH] [Builder] Move extraction of rtlsim depth
---
src/finn/builder/build_dataflow_steps.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index b0f7b6ec6..2ee898bc7 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -666,9 +666,9 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
+ "in FINN C++ verilator driver, falling back to Python"
)
rtlsim_bs = int(cfg.rtlsim_batch_size)
+ orig_rtlsim_trace_depth = get_rtlsim_trace_depth()
if force_python_rtlsim:
# run with single input to get latency
- orig_rtlsim_trace_depth = get_rtlsim_trace_depth()
assert rtlsim_bs > 0, "rtlsim batch size must be >0"
if cfg.verify_save_rtlsim_waveforms:
# set depth to 3 for layer-by-layer visibility
--
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