From 4163a20cfe81afc797c8ca46e9e6389efab8ffdf Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Wed, 22 Dec 2021 23:31:47 +0100
Subject: [PATCH] [Test] switch to ZU3EG as temp workaround for vitis_hls URAM
 pragma bug

---
 tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
index 4d8fa2584..f97b247dd 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
@@ -46,7 +46,7 @@ from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
 from finn.transformation.general import GiveUniqueNodeNames
 from finn.util.basic import gen_finn_dt_tensor
 
-fpga_part = "xc7z020clg400-1"
+fpga_part = "xczu3eg-sbva484-1-e"
 
 
 def make_single_im2col_modelwrapper(
-- 
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