diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 95d6b0c37c1f081527e1bac8d975aa990fcd9ec4..b79850abad8f63ade326103764f6d62121f401cc 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -250,8 +250,6 @@ class MakeZYNQProject(Transformation):
         copy(bitfile_name, deploy_bitfile_name)
         # set bitfile attribute
         model.set_metadata_prop("bitfile", deploy_bitfile_name)
-        # set platform attribute for correct remote execution
-        model.set_metadata_prop("platform", "zynq-iodma")
         hwh_name = (
             vivado_pynq_proj_dir
             + "/finn_zynq_link.srcs/sources_1/bd/top/hw_handoff/top.hwh"
@@ -312,9 +310,12 @@ class ZynqBuild(Transformation):
                     self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True
                 )
             )
+            kernel_model.set_metadata_prop("platform", "zynq-iodma")
             kernel_model.save(dataflow_model_filename)
         # Assemble design from IPs
         model = model.transform(
             MakeZYNQProject(self.platform, enable_debug=self.enable_debug)
         )
+        # set platform attribute for correct remote execution
+        model.set_metadata_prop("platform", "zynq-iodma")
         return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py
index b43df1cfa203aa8d7757ad1d98799fee19edd821..047480897b435a3de0f9746e52aa7c3eb634385c 100644
--- a/src/finn/transformation/fpgadataflow/vitis_build.py
+++ b/src/finn/transformation/fpgadataflow/vitis_build.py
@@ -358,6 +358,7 @@ class VitisBuild(Transformation):
             kernel_model = kernel_model.transform(
                 CreateVitisXO(sdp_node.onnx_node.name)
             )
+            kernel_model.set_metadata_prop("platform", "alveo")
             kernel_model.save(dataflow_model_filename)
         # Assemble design from kernels
         model = model.transform(