From 3e45b6638c584a4b94062499ceb724e8f7199016 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sun, 16 Feb 2020 22:01:46 +0000
Subject: [PATCH] [Test] add test for pyverilate_stitched_ip
---
.../test_fpgadataflow_ip_stitch.py | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index 11b6dc630..1795887f3 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -23,6 +23,7 @@ from finn.util.basic import (
make_build_dir,
pynq_part_map,
)
+from finn.util.fpgadataflow import pyverilate_stitched_ip
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
@@ -207,6 +208,25 @@ def test_fpgadataflow_ipstitch_do_stitch():
model.save(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch.onnx")
+@pytest.mark.dependency(depends=["test_fpgadataflow_ipstitch_do_stitch"])
+def test_fpgadataflow_ipstitch_rtlsim():
+ model = ModelWrapper(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch.onnx")
+ sim = pyverilate_stitched_ip(model)
+ exp_io = [
+ "ap_clk_0",
+ "ap_rst_n_0",
+ "in0_V_V_0_tdata",
+ "in0_V_V_0_tready",
+ "in0_V_V_0_tvalid",
+ "out_r_0_tdata",
+ "out_r_0_tkeep",
+ "out_r_0_tlast",
+ "out_r_0_tready",
+ "out_r_0_tvalid",
+ ]
+ assert dir(sim.io) == exp_io
+
+
@pytest.mark.dependency(depends=["test_fpgadataflow_ipstitch_do_stitch"])
def test_fpgadataflow_ipstitch_pynq_projgen():
model = ModelWrapper(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch.onnx")
--
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