From 3b993cfcea30a8144725e7d74681f3267fcfefe6 Mon Sep 17 00:00:00 2001
From: Georg Streich <streichg@ethz.ch>
Date: Wed, 29 Nov 2023 22:00:47 +0100
Subject: [PATCH] Add interface widths
---
custom_hls/accl/funcs.hpp | 2 +-
docker/Dockerfile.finn | 8 +++---
src/finn/builder/build_dataflow_steps.py | 1 -
src/finn/custom_op/fpgadataflow/accl.py | 3 ---
.../fpgadataflow/create_stitched_ip.py | 26 ++++++++++++++-----
5 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/custom_hls/accl/funcs.hpp b/custom_hls/accl/funcs.hpp
index e113e31f8..e2d0a022d 100644
--- a/custom_hls/accl/funcs.hpp
+++ b/custom_hls/accl/funcs.hpp
@@ -19,6 +19,7 @@ void accl_out(
) {
STREAM<stream_word> data_from_cclo;
+ accl_hls::ACCLCommand accl(cmd_to_cclo, sts_from_cclo, comm_adr, dpcfg_adr, 0, 3);
accl_hls::ACCLData data(data_to_cclo, data_from_cclo);
ap_uint<accl_width> accl_word;
@@ -50,7 +51,6 @@ void accl_out(
data.push(accl_word, 0);
}
- accl_hls::ACCLCommand accl(cmd_to_cclo, sts_from_cclo, comm_adr, dpcfg_adr, 0, 3);
accl.stream_put(num_transfer_bits / 32, 9, destination, 0, false);
#ifdef CPPSIM
diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn
index 8d04653be..cffd18dad 100644
--- a/docker/Dockerfile.finn
+++ b/docker/Dockerfile.finn
@@ -33,10 +33,10 @@ ARG XRT_DEB_VERSION="xrt_202220.2.14.354_22.04-amd64-xrt"
WORKDIR /workspace
-ENV http_proxy http://proxy.ethz.ch:3128
-ENV https_proxy http://proxy.ethz.ch:3128
-ENV HTTPS_PROXY http://proxy.ethz.ch:3128
-ENV HTTP_PROXY http://proxy.ethz.ch:3128
+# ENV http_proxy http://proxy.ethz.ch:3128
+# ENV https_proxy http://proxy.ethz.ch:3128
+# ENV HTTPS_PROXY http://proxy.ethz.ch:3128
+# ENV HTTP_PROXY http://proxy.ethz.ch:3128
# some Vitis deps require a timezone to be specified, which hangs in Docker
# use workaround from https://grigorkh.medium.com/fix-tzdata-hangs-docker-image-build-cdb52cc3360d
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index 8a4a3cfb3..72284cb83 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -638,7 +638,6 @@ def step_create_stitched_ip(model: ModelWrapper, cfg: DataflowBuildConfig):
cfg.synth_clk_period_ns,
vitis=cfg.stitched_ip_gen_dcp,
signature=cfg.signature,
- accl_interface=True,
)
)
# TODO copy all ip sources into output dir? as zip?
diff --git a/src/finn/custom_op/fpgadataflow/accl.py b/src/finn/custom_op/fpgadataflow/accl.py
index 769edaf08..17e71598e 100644
--- a/src/finn/custom_op/fpgadataflow/accl.py
+++ b/src/finn/custom_op/fpgadataflow/accl.py
@@ -255,9 +255,6 @@ class ACCLOut(ACCLOp):
dest = self.get_nodeattr("otherRank")
self.code_gen_dict["$DOCOMPUTE$"] = [
- '''
- while (in0_{}.empty());
- '''.format(self.hls_sname()),
'''
accl_out<{}, {}, {}>(
{},
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 658c5387d..e35c31536 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -43,6 +43,7 @@ from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
)
from finn.util.basic import make_build_dir
from finn.util.fpgadataflow import is_fpgadataflow_node
+from finn.custom_op.fpgadataflow.accl import ACCLOp, accl_word_size
def is_external_input(model, node, i):
@@ -86,7 +87,7 @@ class CreateStitchedIP(Transformation):
The packaged block design IP can be found under the ip subdirectory.
"""
- def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[], accl_interface=False):
+ def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[]):
super().__init__()
self.fpgapart = fpgapart
self.clk_ns = clk_ns
@@ -101,7 +102,6 @@ class CreateStitchedIP(Transformation):
self.clock_reset_are_external = False
self.create_cmds = []
self.connect_cmds = []
- self.accl_interface = accl_interface
# keep track of top-level interface names
self.intf_names = {
"clk": [],
@@ -280,11 +280,13 @@ class CreateStitchedIP(Transformation):
self.connect_cmds.append("assign_bd_address")
def setup_accl_interface(self, model):
- has_accl_in = any(node.op_type == "ACCLIn" for node in model.graph.node)
-
+ # For now we assume that there will always be two unused streams that can be tied
+ # off by connecting them together.
unused_src = None
unused_sink = None
+ has_accl_in = any(node.op_type == "ACCLIn" for node in model.graph.node)
+
if has_accl_in:
self.connect_cmds.append("set_property name data_from_cclo_0 [get_bd_intf_ports s_axis_0]")
self.connect_cmds.append("create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_0")
@@ -344,8 +346,14 @@ class CreateStitchedIP(Transformation):
if accl_out_node is None:
tie_off("sts_from_cclo_0", "cmd_to_cclo_0")
- self.intf_names["s_axis"] += ["sts_from_cclo_0", "data_from_cclo_0"]
- self.intf_names["m_axis"] += ["cmd_from_cclo_0", "data_to_cclo_0"]
+ self.intf_names["s_axis"] += [
+ ("sts_from_cclo_0", 32),
+ ("data_from_cclo_0", accl_word_size)
+ ]
+ self.intf_names["m_axis"] += [
+ ("cmd_from_cclo_0", 32),
+ ("data_to_cclo_0", accl_word_size)
+ ]
def apply(self, model):
# ensure non-relative readmemh .dat files
@@ -417,7 +425,11 @@ class CreateStitchedIP(Transformation):
if node.output[i] == out_name:
self.connect_m_axis_external(node, idx=i)
- if self.accl_interface:
+ has_accl_node = any(
+ issubclass(type(getCustomOp(node)), ACCLOp)
+ for node in model.graph.node
+ )
+ if has_accl_node:
self.setup_accl_interface(model)
if self.signature:
--
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