diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py index f6114ea028817b4248b37572067ed80de8364712..4c38fea70d7e80f6cb17732f7f413bb2afb1b830 100644 --- a/src/finn/custom_op/fpgadataflow/templates.py +++ b/src/finn/custom_op/fpgadataflow/templates.py @@ -137,7 +137,9 @@ reg [31:0] config_d0 = 0; wire [31:0] config_q0; //multiple wire AXI Streams -reg m_axis_0_afull = 0; +reg m_axis_0_afull; +// FIFO count to generate programmable full +wire [5:0] fifo_0_count; wire m_axis_0_tready; wire m_axis_0_tvalid; wire $WEIGHT_RANGE$ m_axis_0_tdata; @@ -257,12 +259,9 @@ mem ); -// two consecutive weight streamer FIFOs to provide the same functionality -// as "programmable full" -// weight streamer FIFO 1 Q_srl #( -.depth(16), +.depth(32), .width($WEIGHT_WIDTH$) ) $LAYER_NAME$_w_fifo_1 @@ -274,25 +273,10 @@ $LAYER_NAME$_w_fifo_1 .i_r(m_axis_0_tready), .o_d(m_axis_0_tdata_q), .o_v(m_axis_0_tvalid_q), - .o_r(m_axis_0_tready_q) + .o_r(m_axis_0_tready_q), + .count(fifo_0_count) ); -// weight streamer FIFO 2 -Q_srl #( -.depth(16), -.width($WEIGHT_WIDTH$) -) -$LAYER_NAME$_w_fifo_2 -( - .clock(ap_clk), - .reset(!ap_rst_n), - .i_d(m_axis_0_tdata_q), - .i_v(m_axis_0_tvalid_q), - .i_r(m_axis_0_tready_q), - .o_d(m_axis_0_tdata_q2), - .o_v(m_axis_0_tvalid_q2), - .o_r(m_axis_0_tready_q2) -); //MVA_Stream_Unit @@ -304,14 +288,16 @@ MVA_Stream_U .in0_V_V_TDATA(in0_V_V_TDATA), //$IN_RANGE$ input .in0_V_V_TVALID(in0_V_V_TVALID), //input .in0_V_V_TREADY(in0_V_V_TREADY), //output -.weights_V_V_TDATA(m_axis_0_tdata_q2), //$WEIGHT_RANGE$ input -.weights_V_V_TVALID(m_axis_0_tvalid_q2), //input -.weights_V_V_TREADY(m_axis_0_tready_q2), //output +.weights_V_V_TDATA(m_axis_0_tdata_q), //$WEIGHT_RANGE$ input +.weights_V_V_TVALID(m_axis_0_tvalid_q), //input +.weights_V_V_TREADY(m_axis_0_tready_q), //output .out_V_V_TDATA(out_V_V_TDATA), //$OUT_RANGE$ output .out_V_V_TVALID(out_V_V_TVALID), //output .out_V_V_TREADY(out_V_V_TREADY) //input ); +// programmable full threshold at 16 elements +assign m_axis_0_afull = (fifo_0_count > 16); endmodule """