From 2a69cab6731f79c174bb45a05e93fabf8d23958b Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Tue, 13 Oct 2020 16:26:49 +0200
Subject: [PATCH] [IPI] allow multiple AXI lite interfaces
---
.../fpgadataflow/create_stitched_ip.py | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 069ceccbc..ddd6607aa 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -65,7 +65,6 @@ class CreateStitchedIP(Transformation):
"""The chosen frequency may lead to failure due to clock divider
constraints."""
)
- self.has_axilite = False
self.has_aximm = False
self.has_m_axis = False
self.m_axis_idx = 0
@@ -127,15 +126,11 @@ class CreateStitchedIP(Transformation):
"make_bd_intf_pins_external "
"[get_bd_intf_pins %s/%s]" % (inst_name, axilite_intf_name[0])
)
- self.connect_cmds.append(
- "set_property name s_axi_control "
- "[get_bd_intf_ports %s_0]" % axilite_intf_name[0]
+ ext_if_name = "%s_%d" % (
+ axilite_intf_name[0],
+ len(self.intf_names["axilite"]),
)
- assert (
- self.has_axilite is False
- ), "Currently limited to one slave AXI-Stream"
- self.intf_names["axilite"] = ["s_axi_control"]
- self.has_axilite = True
+ self.intf_names["axilite"].append(ext_if_name)
if len(aximm_intf_name) != 0:
self.connect_cmds.append(
"make_bd_intf_pins_external [get_bd_intf_pins %s/%s]"
--
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