From 21a3b712b55dccbe15a397d0414c7d35fffbdd23 Mon Sep 17 00:00:00 2001
From: Alessandro Pappalardo <volcacius@users.noreply.github.com>
Date: Tue, 7 Apr 2020 22:46:37 +0100
Subject: [PATCH] Deal gracefully with missing PyVerilator
---
.../custom_op/fpgadataflow/convolutioninputgenerator.py | 8 +++++++-
.../fpgadataflow/streamingdatawidthconverter_batch.py | 8 +++++++-
src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py | 8 +++++++-
src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py | 8 +++++++-
src/finn/util/fpgadataflow.py | 8 +++++++-
5 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index e2a2f90b8..d2588c2c8 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -29,7 +29,10 @@
import os
import numpy as np
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
from finn.core.datatype import DataType
from finn.custom_op.fpgadataflow import HLSCustomOp
@@ -206,6 +209,9 @@ class ConvolutionInputGenerator(HLSCustomOp):
did not produce expected ofolded utput shape"
context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
elif mode == "rtlsim":
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
index ce135e910..1d9a10804 100644
--- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
@@ -28,7 +28,10 @@
import os
import numpy as np
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
from finn.custom_op.fpgadataflow import HLSCustomOp
from finn.core.datatype import DataType
from onnx import TensorProto, helper
@@ -353,6 +356,9 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
context[node.output[0]] = output
elif mode == "rtlsim":
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 00b8287a3..a00402cf1 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -32,7 +32,10 @@ import subprocess
from shutil import copy
import numpy as np
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.custom_op.fpgadataflow import HLSCustomOp
@@ -631,6 +634,9 @@ class StreamingFCLayer_Batch(HLSCustomOp):
oshape = self.get_normal_output_shape()
context[node.output[0]] = context[node.output[0]].reshape(*oshape)
elif mode == "rtlsim":
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
# set top name depending on mem_mode
mem_mode = self.get_nodeattr("mem_mode")
if mem_mode == "const":
diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
index 804da50f5..4f19f2cf1 100644
--- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
@@ -28,7 +28,10 @@
import os
import numpy as np
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
from finn.custom_op.fpgadataflow import HLSCustomOp
from finn.custom_op.im2col import compute_conv_output_dim
from finn.core.datatype import DataType
@@ -301,6 +304,9 @@ class StreamingMaxPool_Batch(HLSCustomOp):
did not produce expected ofolded utput shape"
context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
elif mode == "rtlsim":
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index 29607b002..a32ca4a5d 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -29,7 +29,10 @@
import os
import subprocess
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
class IPGenBuilder:
@@ -69,6 +72,9 @@ class IPGenBuilder:
def pyverilate_stitched_ip(model):
"Given a model with stitched IP, return a PyVerilator sim object."
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
with open(vivado_stitch_proj_dir + "/all_verilog_srcs.txt", "r") as f:
all_verilog_srcs = f.read().split()
--
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