From 217660a938b6c7a9eb691bc4f5012238434eecf0 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 7 Aug 2020 00:20:24 +0200
Subject: [PATCH] [ZYNQ] remove InsertTLastMarker, support stitching w/o
TLastMarker
---
.../transformation/fpgadataflow/create_stitched_ip.py | 11 +++--------
.../transformation/fpgadataflow/make_zynq_proj.py | 4 ----
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 018ad385f..90b4b6c47 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -210,7 +210,8 @@ class CreateStitchedIP(Transformation):
assert (
node_inst.get_nodeattr("Direction") == "in"
), """Output TLastMarker incorrect direction"""
- elif node.op_type == "IODMA":
+ elif node.op_type == "IODMA" and len(model.graph.node) != 1:
+ # don't apply this check for a 1-node partition
assert (
node_inst.get_nodeattr("direction") == "in"
), """Input DMA incorrect direction"""
@@ -241,17 +242,11 @@ class CreateStitchedIP(Transformation):
if model.find_consumers(node.output[0]) is None:
# last node in graph
self.connect_m_axis_external(node)
- # ensure it is a TLastMarker to have a valid TLast signal
- assert (
- node.op_type == "TLastMarker" or node.op_type == "IODMA"
- ), """Last node is not TLastMarker or DMA.
- Please run transformation InsertTLastMarker/InsertIODMA to ensure
- a valid TLast signal"""
if node.op_type == "TLastMarker":
assert (
node_inst.get_nodeattr("Direction") == "out"
), """Output TLastMarker incorrect direction"""
- elif node.op_type == "IODMA":
+ elif node.op_type == "IODMA" and len(model.graph.node) != 1:
assert (
node_inst.get_nodeattr("direction") == "out"
), """Output DMA incorrect direction"""
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 994c41fd0..dfc076ba5 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -41,7 +41,6 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import (
)
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
-from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
@@ -297,9 +296,6 @@ class ZynqBuild(Transformation):
dataflow_model_filename = sdp_node.get_nodeattr("model")
kernel_model = ModelWrapper(dataflow_model_filename)
kernel_model = kernel_model.transform(InsertFIFO())
- kernel_model = kernel_model.transform(
- InsertTLastMarker(both=True, external=False, dynamic=False)
- )
kernel_model = kernel_model.transform(GiveUniqueNodeNames())
kernel_model.save(dataflow_model_filename)
kernel_model = kernel_model.transform(
--
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