diff --git a/docs/finn/example_networks.rst b/docs/finn/example_networks.rst
index e8b29a5fb862f6ebe917327a8f6c96edbf529b96..51089c591be08fbfc8032f91481e63715b55c657 100644
--- a/docs/finn/example_networks.rst
+++ b/docs/finn/example_networks.rst
@@ -15,22 +15,22 @@ The rows in the table are different steps of the FINN end-to-end flow.
If a particular network is supported for a particular step in the current FINN
version, this is indicated by an x mark in the table.
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| FINN step | Basic test | TFC-w1a1 | TFC-w1a2 | CNV-w1a1 | CNV-w1a2 | CNV-w2a2 |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Export/Import | x | x | x | x | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Streamlining | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Convert to HLS layers | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Stitched IP | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Hardware test | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| npysim | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| rtlsim node-by-node | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| rtlsim stitched IP | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| FINN step | Basic test | TFC-w1a1 | TFC-w1a2 | TFC-w2a2 | CNV-w1a1 | CNV-w1a2 | CNV-w2a2 |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Export/Import | x | x | x | x | x | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Streamlining | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Convert to HLS layers | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Stitched IP | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Hardware test | x | x | x | | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| npysim | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| rtlsim node-by-node | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| rtlsim stitched IP | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6b728c0555a4889b8e76d5759233d1109a3002bd
--- /dev/null
+++ b/finn-rtllib/memstream/component.xml
@@ -0,0 +1,1082 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>memstream</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>m_axis_0</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_1</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_2</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_3</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_4</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_5</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>aclk</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:modelName>memstream</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>ba6d3300</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:modelName>memstream</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>54f61a0e</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>92c3ebfc</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>aclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>config_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>config_ce</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>config_we</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>config_d0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>config_q0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_0_afull</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_0_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_0_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_0_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM0_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_1_afull</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_1_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_1_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m_axis_1_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM1_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
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+ <spirit:displayName>Strm3 Offset</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_OFFSET">6912</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STRM4_OFFSET</spirit:name>
+ <spirit:displayName>Strm4 Offset</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_OFFSET">9216</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STRM5_OFFSET</spirit:name>
+ <spirit:displayName>Strm5 Offset</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">artix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">artix7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">kintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">kintex7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">kintexu</xilinx:family>
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+ <xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>memstream_v1_0</xilinx:displayName>
+ <xilinx:definitionSource>package_project</xilinx:definitionSource>
+ <xilinx:coreRevision>2</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2019-11-04T19:37:20Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="nopcore"/>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a3d79be_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ca546af_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2bb0c52f_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1f6f8fe4_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@79ecbc44_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22fd683_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c00346d_ARCHIVE_LOCATION">c:/Users/lucianp/Documents/git/finn-rtllib/memstream</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d8b2551"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5e0c4694"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="cabd7433"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f63127c8"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="5365a08b"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v
new file mode 100644
index 0000000000000000000000000000000000000000..a1c8e066d7290699575c94b0ac939d5a3fb27b19
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream.v
@@ -0,0 +1,465 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module memstream
+#(
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
+ parameter CONFIG_EN = 1,
+ parameter NSTREAMS = 6,//1 up to 6
+
+ parameter MEM_DEPTH = 13824,
+ parameter MEM_WIDTH = 32,
+ parameter MEM_INIT = "./",
+
+ //widths per stream
+ parameter STRM0_WIDTH = 32,
+ parameter STRM1_WIDTH = 32,
+ parameter STRM2_WIDTH = 32,
+ parameter STRM3_WIDTH = 32,
+ parameter STRM4_WIDTH = 32,
+ parameter STRM5_WIDTH = 32,
+
+ //depths per stream
+ parameter STRM0_DEPTH = 2304,
+ parameter STRM1_DEPTH = 2304,
+ parameter STRM2_DEPTH = 2304,
+ parameter STRM3_DEPTH = 2304,
+ parameter STRM4_DEPTH = 2304,
+ parameter STRM5_DEPTH = 2304,
+
+ //offsets for each stream
+ parameter STRM0_OFFSET = 0,
+ parameter STRM1_OFFSET = 2304,
+ parameter STRM2_OFFSET = 4608,
+ parameter STRM3_OFFSET = 6912,
+ parameter STRM4_OFFSET = 9216,
+ parameter STRM5_OFFSET = 11520
+)
+
+(
+ input aclk,
+ input aresetn,
+
+ //optional configuration interface compatible with ap_memory
+ input [31:0] config_address,
+ input config_ce,
+ input config_we,
+ input [31:0] config_d0,
+ output [31:0] config_q0,
+
+ //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
+ input m_axis_0_afull,
+ input m_axis_0_tready,
+ output m_axis_0_tvalid,
+ output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
+
+ input m_axis_1_afull,
+ input m_axis_1_tready,
+ output m_axis_1_tvalid,
+ output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
+
+ input m_axis_2_afull,
+ input m_axis_2_tready,
+ output m_axis_2_tvalid,
+ output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
+
+ input m_axis_3_afull,
+ input m_axis_3_tready,
+ output m_axis_3_tvalid,
+ output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
+
+ input m_axis_4_afull,
+ input m_axis_4_tready,
+ output m_axis_4_tvalid,
+ output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
+
+ input m_axis_5_afull,
+ input m_axis_5_tready,
+ output m_axis_5_tvalid,
+ output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
+
+
+);
+
+//calculate number of RAMB18 blocks we need depth-wise
+localparam NMEMBLOCKS = (MEM_DEPTH+1023) / 1024; //ceil(MEM_DEPTH/1024)
+
+//calculate width of address for each block
+localparam BLOCKADRWIDTH = NMEMBLOCKS > 1 ? 10 : $clog2(MEM_DEPTH);
+
+//determine whether a stream needs to multiplex between memory blocks
+localparam STRM0_MUX = ((STRM0_OFFSET/1024) != ((STRM0_OFFSET+STRM0_DEPTH)/1024));
+localparam STRM1_MUX = ((STRM1_OFFSET/1024) != ((STRM1_OFFSET+STRM1_DEPTH)/1024));
+localparam STRM2_MUX = ((STRM2_OFFSET/1024) != ((STRM2_OFFSET+STRM2_DEPTH)/1024));
+localparam STRM3_MUX = ((STRM3_OFFSET/1024) != ((STRM3_OFFSET+STRM3_DEPTH)/1024));
+localparam STRM4_MUX = ((STRM4_OFFSET/1024) != ((STRM4_OFFSET+STRM4_DEPTH)/1024));
+localparam STRM5_MUX = ((STRM5_OFFSET/1024) != ((STRM5_OFFSET+STRM5_DEPTH)/1024));
+
+//determine what the base block of each stream is
+localparam STRM0_BLOCK = (STRM0_OFFSET/1024);
+localparam STRM1_BLOCK = (STRM1_OFFSET/1024);
+localparam STRM2_BLOCK = (STRM2_OFFSET/1024);
+localparam STRM3_BLOCK = (STRM3_OFFSET/1024);
+localparam STRM4_BLOCK = (STRM4_OFFSET/1024);
+localparam STRM5_BLOCK = (STRM5_OFFSET/1024);
+
+//determine what the end block of each stream is
+localparam STRM0_END_BLOCK = ((STRM0_OFFSET+STRM0_DEPTH-1)/1024);
+localparam STRM1_END_BLOCK = ((STRM1_OFFSET+STRM1_DEPTH-1)/1024);
+localparam STRM2_END_BLOCK = ((STRM2_OFFSET+STRM2_DEPTH-1)/1024);
+localparam STRM3_END_BLOCK = ((STRM3_OFFSET+STRM3_DEPTH-1)/1024);
+localparam STRM4_END_BLOCK = ((STRM4_OFFSET+STRM4_DEPTH-1)/1024);
+localparam STRM5_END_BLOCK = ((STRM5_OFFSET+STRM5_DEPTH-1)/1024);
+
+//determine the number of blocks spanned by each stream
+localparam STRM0_NBLOCKS = STRM0_END_BLOCK - STRM0_BLOCK + 1;
+localparam STRM1_NBLOCKS = STRM1_END_BLOCK - STRM1_BLOCK + 1;
+localparam STRM2_NBLOCKS = STRM2_END_BLOCK - STRM2_BLOCK + 1;
+localparam STRM3_NBLOCKS = STRM3_END_BLOCK - STRM3_BLOCK + 1;
+localparam STRM4_NBLOCKS = STRM4_END_BLOCK - STRM4_BLOCK + 1;
+localparam STRM5_NBLOCKS = STRM5_END_BLOCK - STRM5_BLOCK + 1;
+
+//TODO: check that memory width is equal to the widest stream
+//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
+initial begin
+ if((NSTREAMS < 1) | (NSTREAMS > 6)) begin
+ $display("Invalid setting for NSTREAMS, please set in range [1,6]");
+ $finish();
+ end
+end
+
+//invert reset
+wire rst;
+assign rst = ~aresetn;
+
+//WARNING: pipeline depth is larger than the number of streams per port so we have in-flight writes that may see not-ready when they get executed
+//solution: use prog-full to make sure we have an equal number of free slots in the stream to the read pipeline depth
+
+reg [$clog2(MEM_DEPTH)-1:0] strm0_addr = STRM0_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm1_addr = STRM1_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm2_addr = STRM2_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm3_addr = STRM3_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm4_addr = STRM4_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm5_addr = STRM5_OFFSET;
+
+reg strm0_incr_en;
+reg strm1_incr_en;
+reg strm2_incr_en;
+reg strm3_incr_en;
+reg strm4_incr_en;
+reg strm5_incr_en;
+
+wire strm0_rst;
+wire strm1_rst;
+wire strm2_rst;
+wire strm3_rst;
+wire strm4_rst;
+wire strm5_rst;
+
+reg strm0_ready;
+reg strm1_ready;
+reg strm2_ready;
+reg strm3_ready;
+reg strm4_ready;
+reg strm5_ready;
+
+//arbiter: work on one stream at a time
+//multiplex each port between (up to) half of the streams
+reg [1:0] current_stream_porta = 0;
+reg [1:0] current_stream_portb = 0;
+
+always @(posedge aclk) begin
+ if(rst)
+ current_stream_porta <= 0;
+ else case(current_stream_porta)
+ 0: current_stream_porta <= strm2_ready ? 1 : strm4_ready ? 2 : 0;
+ 1: current_stream_porta <= strm4_ready ? 2 : strm0_ready ? 0 : 1;
+ 2: current_stream_porta <= strm0_ready ? 0 : strm2_ready ? 1 : 2;
+ endcase
+ if(rst)
+ current_stream_portb <= 0;
+ else case(current_stream_portb)
+ 0: current_stream_portb <= strm3_ready ? 1 : strm5_ready ? 2 : 0;
+ 1: current_stream_portb <= strm5_ready ? 2 : strm1_ready ? 0 : 1;
+ 2: current_stream_portb <= strm1_ready ? 0 : strm3_ready ? 1 : 2;
+ endcase
+end
+
+always @(posedge aclk) begin
+ if(rst) begin
+ strm0_incr_en <= 0;
+ strm1_incr_en <= 0;
+ strm2_incr_en <= 0;
+ strm3_incr_en <= 0;
+ strm4_incr_en <= 0;
+ strm5_incr_en <= 0;
+ end else begin
+ strm0_incr_en <= (current_stream_porta == 0) & strm0_ready;
+ strm1_incr_en <= (current_stream_portb == 0) & strm1_ready;
+ strm2_incr_en <= (current_stream_porta == 1) & strm2_ready;
+ strm3_incr_en <= (current_stream_portb == 1) & strm3_ready;
+ strm4_incr_en <= (current_stream_porta == 2) & strm4_ready;
+ strm5_incr_en <= (current_stream_portb == 2) & strm5_ready;
+ end
+end
+
+assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
+assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
+assign strm2_rst = strm2_incr_en & (strm2_addr == (STRM2_OFFSET + STRM2_DEPTH-1));
+assign strm3_rst = strm3_incr_en & (strm3_addr == (STRM3_OFFSET + STRM3_DEPTH-1));
+assign strm4_rst = strm4_incr_en & (strm4_addr == (STRM4_OFFSET + STRM4_DEPTH-1));
+assign strm5_rst = strm5_incr_en & (strm5_addr == (STRM5_OFFSET + STRM5_DEPTH-1));
+
+always @(posedge aclk) begin
+ strm0_ready <= ~m_axis_0_afull;
+ strm1_ready <= ~m_axis_1_afull & (NSTREAMS >= 2);
+ strm2_ready <= ~m_axis_2_afull & (NSTREAMS >= 3);
+ strm3_ready <= ~m_axis_3_afull & (NSTREAMS >= 4);
+ strm4_ready <= ~m_axis_4_afull & (NSTREAMS >= 5);
+ strm5_ready <= ~m_axis_5_afull & (NSTREAMS >= 6);
+end
+
+//one address counter per stream; more LUTs but keeps routing short and local
+always @(posedge aclk) begin
+ if(strm0_rst | rst)
+ strm0_addr <= STRM0_OFFSET;
+ else if(strm0_incr_en)
+ strm0_addr <= strm0_addr + 1;
+ if(strm1_rst | rst)
+ strm1_addr <= STRM1_OFFSET;
+ else if(strm1_incr_en)
+ strm1_addr <= strm1_addr + 1;
+ if(strm2_rst | rst)
+ strm2_addr <= STRM2_OFFSET;
+ else if(strm2_incr_en)
+ strm2_addr <= strm2_addr + 1;
+ if(strm3_rst | rst)
+ strm3_addr <= STRM3_OFFSET;
+ else if(strm3_incr_en)
+ strm3_addr <= strm3_addr + 1;
+ if(strm4_rst | rst)
+ strm4_addr <= STRM4_OFFSET;
+ else if(strm4_incr_en)
+ strm4_addr <= strm4_addr + 1;
+ if(strm5_rst | rst)
+ strm5_addr <= STRM5_OFFSET;
+ else if(strm5_incr_en)
+ strm5_addr <= strm5_addr + 1;
+end
+
+reg [$clog2(MEM_DEPTH)-1:0] addra;
+wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqa;
+
+reg [$clog2(MEM_DEPTH)-1:0] addrb;
+wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqb;
+
+wire [NMEMBLOCKS-1:0] we;
+
+reg [1:0] addr_select_porta;
+reg [1:0] addr_select_portb;
+
+//multiplex addresses of various streams into address ports of memory
+always @(posedge aclk) begin
+ addr_select_porta <= current_stream_porta;
+ case(addr_select_porta)
+ 0: addra <= strm0_addr;
+ 1: addra <= strm2_addr;
+ 2: addra <= strm4_addr;
+ endcase
+ addr_select_portb <= current_stream_portb;
+ case(addr_select_portb)
+ 0: addrb <= strm1_addr;
+ 1: addrb <= strm3_addr;
+ 2: addrb <= strm5_addr;
+ endcase
+end
+
+genvar g;
+generate for(g=0; g<NMEMBLOCKS; g=g+1) begin: blockports
+
+assign we[g] = (CONFIG_EN == 1) & config_ce & config_we & (config_address[31:BLOCKADRWIDTH] == g);
+
+ramb18_wf_dualport
+#(
+ .ID(g),
+ .DWIDTH(MEM_WIDTH),
+ .AWIDTH(BLOCKADRWIDTH),
+ .MEM_INIT(MEM_INIT)
+)
+ram
+(
+ .clk(aclk),
+
+ .wea(we[g]),
+ .addra(we[g] ? config_address[BLOCKADRWIDTH-1:0] : addra[BLOCKADRWIDTH-1:0]),
+ .wdataa(config_d0),
+ .rdqa(rdqa[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH]),
+
+ .web(1'b0),
+ .addrb(addrb[BLOCKADRWIDTH-1:0]),
+ .wdatab('d0),
+ .rdqb(rdqb[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH])
+);
+
+end
+endgenerate
+
+integer i;
+
+generate if(NMEMBLOCKS > 1) begin: multiblock
+
+wire [MEM_WIDTH-1:0] rdqmux[5:0];
+
+reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblocka[2:0];
+reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblockb[2:0];
+
+always @(posedge aclk) begin
+ rdblocka[0] <= addra[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
+ rdblockb[0] <= addrb[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
+ for(i=0; i<2; i=i+1) begin
+ rdblocka[i+1] <= rdblocka[i];
+ rdblockb[i+1] <= rdblockb[i];
+ end
+end
+
+if(NSTREAMS >= 1) begin: en_strm0
+ if(STRM0_MUX == 1) begin: mux0
+ mux #(STRM0_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM0_BLOCK+STRM0_NBLOCKS)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH],rdqmux[0],rdblocka[1] - STRM0_BLOCK);
+ end else begin: nomux0
+ assign rdqmux[0] = rdqa[(STRM0_BLOCK+1)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_0_tdata = rdqmux[0][STRM0_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 2) begin: en_strm1
+ if(STRM1_MUX == 1) begin: mux1
+ mux #(STRM1_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM1_BLOCK+STRM1_NBLOCKS)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH],rdqmux[1],rdblockb[1] - STRM1_BLOCK);
+ end else begin: nomux1
+ assign rdqmux[1] = rdqb[(STRM1_BLOCK+1)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_1_tdata = rdqmux[1][STRM1_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 3) begin: en_strm2
+ if(STRM2_MUX == 1) begin: mux2
+ mux #(STRM2_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM2_BLOCK+STRM2_NBLOCKS)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH],rdqmux[2],rdblocka[1] - STRM2_BLOCK);
+ end else begin: nomux2
+ assign rdqmux[2] = rdqa[(STRM2_BLOCK+1)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_2_tdata = rdqmux[2][STRM2_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 4) begin: en_strm3
+ if(STRM3_MUX == 1) begin: mux3
+ mux #(STRM3_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM3_BLOCK+STRM3_NBLOCKS)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH],rdqmux[3],rdblockb[1] - STRM3_BLOCK);
+ end else begin: nomux3
+ assign rdqmux[3] = rdqb[(STRM3_BLOCK+1)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_3_tdata = rdqmux[3][STRM3_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 5) begin: en_strm4
+ if(STRM4_MUX == 1) begin: mux4
+ mux #(STRM4_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM4_BLOCK+STRM4_NBLOCKS)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH],rdqmux[4],rdblocka[1] - STRM4_BLOCK);
+ end else begin: nomux4
+ assign rdqmux[4] = rdqa[(STRM4_BLOCK+1)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_4_tdata = rdqmux[4][STRM4_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 6) begin: en_strm5
+ if(STRM5_MUX == 1) begin: mux5
+ mux #(STRM5_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM5_BLOCK+STRM5_NBLOCKS)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH],rdqmux[5],rdblockb[1] - STRM5_BLOCK);
+ end else begin: nomux5
+ assign rdqmux[5] = rdqb[(STRM5_BLOCK+1)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_5_tdata = rdqmux[5][STRM5_WIDTH-1:0];
+end
+
+end else begin: singleblock
+
+if(NSTREAMS >= 1) begin: en_strm0_direct
+ assign m_axis_0_tdata = rdqa[STRM0_WIDTH-1:0];
+end
+if(NSTREAMS >= 2) begin: en_strm1_direct
+ assign m_axis_1_tdata = rdqb[STRM1_WIDTH-1:0];
+end
+if(NSTREAMS >= 3) begin: en_strm2_direct
+ assign m_axis_2_tdata = rdqa[STRM2_WIDTH-1:0];
+end
+if(NSTREAMS >= 4) begin: en_strm3_direct
+ assign m_axis_3_tdata = rdqb[STRM3_WIDTH-1:0];
+end
+if(NSTREAMS >= 5) begin: en_strm4_direct
+ assign m_axis_4_tdata = rdqa[STRM4_WIDTH-1:0];
+end
+if(NSTREAMS >= 6) begin: en_strm5_direct
+ assign m_axis_5_tdata = rdqb[STRM5_WIDTH-1:0];
+end
+
+end
+endgenerate
+
+//output to AXI Streams
+reg tvalid_pipe0[2:0];
+reg tvalid_pipe1[2:0];
+reg tvalid_pipe2[2:0];
+reg tvalid_pipe3[2:0];
+reg tvalid_pipe4[2:0];
+reg tvalid_pipe5[2:0];
+
+assign m_axis_0_tvalid = tvalid_pipe0[2];
+assign m_axis_1_tvalid = tvalid_pipe1[2];
+assign m_axis_2_tvalid = tvalid_pipe2[2];
+assign m_axis_3_tvalid = tvalid_pipe3[2];
+assign m_axis_4_tvalid = tvalid_pipe4[2];
+assign m_axis_5_tvalid = tvalid_pipe5[2];
+
+
+always @(posedge aclk) begin
+ tvalid_pipe0[0] <= strm0_incr_en;
+ tvalid_pipe1[0] <= strm1_incr_en;
+ tvalid_pipe2[0] <= strm2_incr_en;
+ tvalid_pipe3[0] <= strm3_incr_en;
+ tvalid_pipe4[0] <= strm4_incr_en;
+ tvalid_pipe5[0] <= strm5_incr_en;
+ for(i=0; i<2; i=i+1) begin: srl
+ tvalid_pipe0[i+1] <= tvalid_pipe0[i];
+ tvalid_pipe1[i+1] <= tvalid_pipe1[i];
+ tvalid_pipe2[i+1] <= tvalid_pipe2[i];
+ tvalid_pipe3[i+1] <= tvalid_pipe3[i];
+ tvalid_pipe4[i+1] <= tvalid_pipe4[i];
+ tvalid_pipe5[i+1] <= tvalid_pipe5[i];
+ end
+end
+
+assign config_q0 = 0;
+
+endmodule
\ No newline at end of file
diff --git a/finn-rtllib/memstream/hdl/mux.v b/finn-rtllib/memstream/hdl/mux.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5b89aeb4e7eb7b2858d062c18b693d9bd685fb2
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/mux.v
@@ -0,0 +1,44 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module mux
+#(
+ parameter NINPUTS = 1,
+ parameter WIDTH = 16
+)
+(
+ input [NINPUTS*WIDTH-1:0] in,
+ output [WIDTH-1:0] out,
+ input [$clog2(NINPUTS)-1:0] sel
+);
+
+assign out = in >> (sel*WIDTH);
+
+endmodule
\ No newline at end of file
diff --git a/finn-rtllib/memstream/hdl/ramb18.v b/finn-rtllib/memstream/hdl/ramb18.v
new file mode 100644
index 0000000000000000000000000000000000000000..7b207fbd6db7c9d985ba3ed50d7fcd97612e07f5
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/ramb18.v
@@ -0,0 +1,86 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module ramb18_wf_dualport
+#(
+ parameter ID = 0,
+ parameter DWIDTH = 18,
+ parameter AWIDTH = 10,
+ parameter MEM_INIT = ""
+)
+(
+ input clk,
+
+ input wea,
+ input [AWIDTH-1:0] addra,
+ input [DWIDTH-1:0] wdataa,
+ output reg [DWIDTH-1:0] rdqa,
+
+ input web,
+ input [AWIDTH-1:0] addrb,
+ input [DWIDTH-1:0] wdatab,
+ output reg [DWIDTH-1:0] rdqb
+);
+
+(* ram_style = "block" *) reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+reg [DWIDTH-1:0] rdataa;
+reg [DWIDTH-1:0] rdatab;
+
+reg [7:0] idx = ID;
+//initialize memory
+initial begin
+ //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
+ //ID can go up to 99
+ if (ID < 0 && ID > 99) begin
+ $display("ID out of range [0-99]");
+ $finish();
+ end
+ //MEM_INIT path must be terminated by /
+ if (ID < 10)
+ $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, 1023);
+ else
+ $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, 1023);
+end
+
+//memory ports, with output pipeline register
+always @(posedge clk) begin
+ if(wea)
+ mem[addra] <= wdataa;
+ rdataa <= mem[addra];
+ rdqa <= rdataa;
+end
+always @(posedge clk) begin
+ if(web)
+ mem[addrb] <= wdatab;
+ rdatab <= mem[addrb];
+ rdqb <= rdatab;
+end
+
+endmodule
\ No newline at end of file
diff --git a/finn-rtllib/memstream/sim/gen_memblocks.sh b/finn-rtllib/memstream/sim/gen_memblocks.sh
new file mode 100644
index 0000000000000000000000000000000000000000..05962f7be8fe4afd7790640cf4d280600dcf43d1
--- /dev/null
+++ b/finn-rtllib/memstream/sim/gen_memblocks.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+NLINES=`cat $1 | wc -l`
+NBLOCKS=$(( ($NLINES + 1023) / 1024 ))
+rm memblock_*.dat
+
+for (( i=0; i<$NBLOCKS; i++ ))
+do
+ START=$(( 1 + $i * 1024 ))
+ tail -n +$START $1 | head -n 1024 >> memblock_$i.dat
+done
\ No newline at end of file
diff --git a/finn-rtllib/memstream/sim/golden.dat b/finn-rtllib/memstream/sim/golden.dat
new file mode 100644
index 0000000000000000000000000000000000000000..1466271bcab961f742e242aea4241a4ffad02828
--- /dev/null
+++ b/finn-rtllib/memstream/sim/golden.dat
@@ -0,0 +1,9216 @@
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diff --git a/finn-rtllib/memstream/sim/tb_memstream.v b/finn-rtllib/memstream/sim/tb_memstream.v
new file mode 100644
index 0000000000000000000000000000000000000000..d63fa30046d7c5f2c50f509174b4937374e70c13
--- /dev/null
+++ b/finn-rtllib/memstream/sim/tb_memstream.v
@@ -0,0 +1,369 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+`timescale 1ns/10ps
+
+module tb_memstream;
+
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
+parameter CONFIG_EN = 1;
+parameter NSTREAMS = 4;//1 up to 6
+
+parameter MEM_DEPTH = 9216;
+parameter MEM_WIDTH = 32;
+parameter MEM_INIT = "./";
+parameter MEM_CHECK = "golden.dat";
+
+//widths per stream
+parameter STRM0_WIDTH = 32;
+parameter STRM1_WIDTH = 32;
+parameter STRM2_WIDTH = 32;
+parameter STRM3_WIDTH = 32;
+parameter STRM4_WIDTH = 1;
+parameter STRM5_WIDTH = 1;
+
+//depths per stream
+parameter STRM0_DEPTH = 2304;
+parameter STRM1_DEPTH = 2304;
+parameter STRM2_DEPTH = 2304;
+parameter STRM3_DEPTH = 2304;
+parameter STRM4_DEPTH = 1;
+parameter STRM5_DEPTH = 1;
+
+//offsets for each stream
+parameter STRM0_OFFSET = 0;
+parameter STRM1_OFFSET = 2304;
+parameter STRM2_OFFSET = 4608;
+parameter STRM3_OFFSET = 6912;
+parameter STRM4_OFFSET = 0;
+parameter STRM5_OFFSET = 0;
+
+
+reg clk;
+reg rst;
+
+reg [31:0] config_address = 0;
+reg config_ce = 0;
+reg config_we = 0;
+reg [31:0] config_d0 = 0;
+wire [31:0] config_q0;
+
+//multiple wire AXI Streams
+reg m_axis_0_afull;
+reg m_axis_0_tready;
+wire m_axis_0_tvalid;
+wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
+
+reg m_axis_1_afull;
+reg m_axis_1_tready;
+wire m_axis_1_tvalid;
+wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
+
+reg m_axis_2_afull;
+reg m_axis_2_tready;
+wire m_axis_2_tvalid;
+wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
+
+reg m_axis_3_afull;
+reg m_axis_3_tready;
+wire m_axis_3_tvalid;
+wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
+
+reg m_axis_4_afull;
+reg m_axis_4_tready;
+wire m_axis_4_tvalid;
+wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
+
+reg m_axis_5_afull;
+reg m_axis_5_tready;
+wire m_axis_5_tvalid;
+wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
+
+reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
+integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
+integer done = 0;
+reg [5:0] rng;
+
+//clock
+initial begin
+ clk = 0;
+ forever #5 clk = ~clk;
+end
+
+initial begin
+ rst = 1;
+ config_ce = 0;
+ m_axis_0_afull = 0;
+ m_axis_1_afull = 0;
+ m_axis_2_afull = 0;
+ m_axis_3_afull = 0;
+ m_axis_4_afull = 0;
+ m_axis_5_afull = 0;
+ m_axis_0_tready = 1;
+ m_axis_1_tready = 1;
+ m_axis_2_tready = 1;
+ m_axis_3_tready = 1;
+ m_axis_4_tready = 1;
+ m_axis_5_tready = 1;
+ repeat(100) @(negedge clk);
+ rst = 0;
+ #100
+ fork
+ begin
+ $display("Starting to generate random AFULL");
+ while(~done) begin
+ rng = $random;
+ m_axis_0_afull = rng[0];
+ m_axis_1_afull = rng[1];
+ m_axis_2_afull = rng[2];
+ m_axis_3_afull = rng[3];
+ m_axis_4_afull = rng[4];
+ m_axis_5_afull = rng[5];
+ @(negedge clk);
+ end
+ end
+ join
+end
+
+
+//DUT
+memstream
+#(
+ CONFIG_EN,
+ NSTREAMS,
+ MEM_DEPTH,
+ MEM_WIDTH,
+ MEM_INIT,
+
+ //widths per stream
+ STRM0_WIDTH,
+ STRM1_WIDTH,
+ STRM2_WIDTH,
+ STRM3_WIDTH,
+ STRM4_WIDTH,
+ STRM5_WIDTH,
+
+ //depths per stream
+ STRM0_DEPTH,
+ STRM1_DEPTH,
+ STRM2_DEPTH,
+ STRM3_DEPTH,
+ STRM4_DEPTH,
+ STRM5_DEPTH,
+
+ //offsets for each stream
+ STRM0_OFFSET,
+ STRM1_OFFSET,
+ STRM2_OFFSET,
+ STRM3_OFFSET,
+ STRM4_OFFSET,
+ STRM5_OFFSET
+)
+dut
+(
+ clk,
+ ~rst,
+
+ //optional AXI-Lite interface
+ config_address,
+ config_ce,
+ config_we,
+ config_d0,
+ config_q0,
+
+ //multiple output AXI Streams
+ m_axis_0_afull,
+ m_axis_0_tready,
+ m_axis_0_tvalid,
+ m_axis_0_tdata,
+
+ m_axis_1_afull,
+ m_axis_1_tready,
+ m_axis_1_tvalid,
+ m_axis_1_tdata,
+
+ m_axis_2_afull,
+ m_axis_2_tready,
+ m_axis_2_tvalid,
+ m_axis_2_tdata,
+
+ m_axis_3_afull,
+ m_axis_3_tready,
+ m_axis_3_tvalid,
+ m_axis_3_tdata,
+
+ m_axis_4_afull,
+ m_axis_4_tready,
+ m_axis_4_tvalid,
+ m_axis_4_tdata,
+
+ m_axis_5_afull,
+ m_axis_5_tready,
+ m_axis_5_tvalid,
+ m_axis_5_tdata
+
+
+);
+
+//stream checkers
+initial begin
+ ptr0 = STRM0_OFFSET;
+ ptr1 = STRM1_OFFSET;
+ ptr2 = STRM2_OFFSET;
+ ptr3 = STRM3_OFFSET;
+ ptr4 = STRM4_OFFSET;
+ ptr5 = STRM5_OFFSET;
+ fork
+ //check stream 0
+ begin
+ $display("Starting stream 0 checker");
+ while(~done & (NSTREAMS > 0)) begin
+ @(negedge clk);
+ if(m_axis_0_tvalid) begin
+ if(m_axis_0_tdata != golden[ptr0]) begin
+ $display("Mismatch on stream 0");
+ $stop();
+ end
+ //increment pointer
+ ptr0 = ptr0 + 1;
+ //rewind pointer if it's reached end
+ if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
+ ptr0 = STRM0_OFFSET;
+ end
+ end
+ end
+ //check stream 1
+ begin
+ $display("Starting stream 1 checker");
+ while(~done & (NSTREAMS > 1)) begin
+ @(negedge clk);
+ if(m_axis_1_tvalid) begin
+ if(m_axis_1_tdata != golden[ptr1]) begin
+ $display("Mismatch on stream 1");
+ $stop();
+ end
+ //increment pointer
+ ptr1 = ptr1 + 1;
+ //rewind pointer if it's reached end
+ if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
+ ptr1 = STRM1_OFFSET;
+ end
+ end
+ end
+
+ //check stream 2
+ begin
+ $display("Starting stream 2 checker");
+ while(~done & (NSTREAMS > 2)) begin
+ @(negedge clk);
+ if(m_axis_2_tvalid) begin
+ if(m_axis_2_tdata != golden[ptr2]) begin
+ $display("Mismatch on stream 2");
+ $stop();
+ end
+ //increment pointer
+ ptr2 = ptr2 + 1;
+ //rewind pointer if it's reached end
+ if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
+ ptr2 = STRM2_OFFSET;
+ end
+ end
+ end
+ //check stream 3
+ begin
+ $display("Starting stream 3 checker");
+ while(~done & (NSTREAMS > 3)) begin
+ @(negedge clk);
+ if(m_axis_3_tvalid) begin
+ if(m_axis_3_tdata != golden[ptr3]) begin
+ $display("Mismatch on stream 3");
+ $stop();
+ end
+ //increment pointer
+ ptr3 = ptr3 + 1;
+ //rewind pointer if it's reached end
+ if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
+ ptr3 = STRM3_OFFSET;
+ end
+ end
+ end
+ //check stream 4
+ begin
+ $display("Starting stream 4 checker");
+ while(~done & (NSTREAMS > 4)) begin
+ @(negedge clk);
+ if(m_axis_4_tvalid) begin
+ if(m_axis_4_tdata != golden[ptr4]) begin
+ $display("Mismatch on stream 4");
+ $stop();
+ end
+ //increment pointer
+ ptr4 = ptr4 + 1;
+ //rewind pointer if it's reached end
+ if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
+ ptr4 = STRM4_OFFSET;
+ end
+ end
+ end
+ //check stream 5
+ begin
+ $display("Starting stream 5 checker");
+ while(~done & (NSTREAMS > 5)) begin
+ @(negedge clk);
+ if(m_axis_5_tvalid) begin
+ if(m_axis_5_tdata != golden[ptr5]) begin
+ $display("Mismatch on stream 5");
+ $stop();
+ end
+ //increment pointer
+ ptr5 = ptr5 + 1;
+ //rewind pointer if it's reached end
+ if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
+ ptr5 = STRM5_OFFSET;
+ end
+ end
+ end
+ join
+end
+
+initial begin
+ done = 0;
+ $readmemh(MEM_CHECK,golden);
+// $dumpfile("wave.vcd");
+// $dumpvars(0,tb_memstream);
+ @(negedge rst);
+ #10000000
+ $display("Test done!");
+ done = 1;
+ #1000
+ $finish();
+end
+
+endmodule
diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh
new file mode 100644
index 0000000000000000000000000000000000000000..24767edf4ade1c6867e0c7d906e7a45bbcb987a2
--- /dev/null
+++ b/finn-rtllib/memstream/sim/test.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+./gen_memblocks.sh golden.dat
+iverilog ../hdl/*.v *v -o sim
+./sim
+
diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e5cbb670da94612e8de73f48cfa4562f89e124d1
--- /dev/null
+++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
@@ -0,0 +1,383 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to validate CONFIG_EN
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to update MEM_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to validate MEM_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
+ # Procedure called to update MEM_INIT when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
+ # Procedure called to validate MEM_INIT
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to update MEM_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to validate MEM_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
+ # Procedure called to update NSTREAMS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
+ # Procedure called to validate NSTREAMS
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to update STRM0_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to validate STRM0_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to update STRM0_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to validate STRM0_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to update STRM0_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to validate STRM0_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to update STRM1_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to validate STRM1_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to update STRM1_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to validate STRM1_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to update STRM1_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to validate STRM1_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to update STRM2_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to validate STRM2_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to update STRM2_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to validate STRM2_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to update STRM2_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to validate STRM2_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to update STRM3_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to validate STRM3_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to update STRM3_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to validate STRM3_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to update STRM3_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to validate STRM3_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to update STRM4_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to validate STRM4_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to update STRM4_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to validate STRM4_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to update STRM4_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to validate STRM4_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to update STRM5_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to validate STRM5_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to update STRM5_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to validate STRM5_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to update STRM5_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to validate STRM5_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.CONFIG_EN { MODELPARAM_VALUE.CONFIG_EN PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.CONFIG_EN}] ${MODELPARAM_VALUE.CONFIG_EN}
+}
+
+proc update_MODELPARAM_VALUE.NSTREAMS { MODELPARAM_VALUE.NSTREAMS PARAM_VALUE.NSTREAMS } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.NSTREAMS}] ${MODELPARAM_VALUE.NSTREAMS}
+}
+
+proc update_MODELPARAM_VALUE.MEM_DEPTH { MODELPARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_DEPTH}] ${MODELPARAM_VALUE.MEM_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.MEM_WIDTH { MODELPARAM_VALUE.MEM_WIDTH PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_WIDTH}] ${MODELPARAM_VALUE.MEM_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.MEM_INIT { MODELPARAM_VALUE.MEM_INIT PARAM_VALUE.MEM_INIT } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_INIT}] ${MODELPARAM_VALUE.MEM_INIT}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_WIDTH { MODELPARAM_VALUE.STRM0_WIDTH PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_WIDTH}] ${MODELPARAM_VALUE.STRM0_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_WIDTH { MODELPARAM_VALUE.STRM1_WIDTH PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_WIDTH}] ${MODELPARAM_VALUE.STRM1_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_WIDTH { MODELPARAM_VALUE.STRM2_WIDTH PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_WIDTH}] ${MODELPARAM_VALUE.STRM2_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_WIDTH { MODELPARAM_VALUE.STRM3_WIDTH PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_WIDTH}] ${MODELPARAM_VALUE.STRM3_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_WIDTH { MODELPARAM_VALUE.STRM4_WIDTH PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_WIDTH}] ${MODELPARAM_VALUE.STRM4_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_WIDTH { MODELPARAM_VALUE.STRM5_WIDTH PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_WIDTH}] ${MODELPARAM_VALUE.STRM5_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_DEPTH { MODELPARAM_VALUE.STRM0_DEPTH PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_DEPTH}] ${MODELPARAM_VALUE.STRM0_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_DEPTH { MODELPARAM_VALUE.STRM1_DEPTH PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_DEPTH}] ${MODELPARAM_VALUE.STRM1_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_DEPTH { MODELPARAM_VALUE.STRM2_DEPTH PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_DEPTH}] ${MODELPARAM_VALUE.STRM2_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_DEPTH { MODELPARAM_VALUE.STRM3_DEPTH PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_DEPTH}] ${MODELPARAM_VALUE.STRM3_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_DEPTH { MODELPARAM_VALUE.STRM4_DEPTH PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_DEPTH}] ${MODELPARAM_VALUE.STRM4_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_DEPTH { MODELPARAM_VALUE.STRM5_DEPTH PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_DEPTH}] ${MODELPARAM_VALUE.STRM5_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_OFFSET { MODELPARAM_VALUE.STRM0_OFFSET PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_OFFSET}] ${MODELPARAM_VALUE.STRM0_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_OFFSET { MODELPARAM_VALUE.STRM1_OFFSET PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_OFFSET}] ${MODELPARAM_VALUE.STRM1_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_OFFSET { MODELPARAM_VALUE.STRM2_OFFSET PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_OFFSET}] ${MODELPARAM_VALUE.STRM2_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_OFFSET { MODELPARAM_VALUE.STRM3_OFFSET PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_OFFSET}] ${MODELPARAM_VALUE.STRM3_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_OFFSET { MODELPARAM_VALUE.STRM4_OFFSET PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_OFFSET}] ${MODELPARAM_VALUE.STRM4_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET}
+}
+
diff --git a/src/finn/transformation/streamline/absorb.py b/src/finn/transformation/streamline/absorb.py
index eb5845f198bc636e85d395b7bdf32e01b0222cf2..5a9355bcfefc57f9608490a156906e65f7672271 100644
--- a/src/finn/transformation/streamline/absorb.py
+++ b/src/finn/transformation/streamline/absorb.py
@@ -161,6 +161,7 @@ class Absorb1BitMulIntoMatMul(Transformation):
if n.op_type == "MatMul":
matmul_weight_name = n.input[1]
W = model.get_initializer(matmul_weight_name)
+ Wdt = model.get_tensor_datatype(matmul_weight_name)
assert W is not None, "Initializer for matmul weights is not set."
consumer = model.find_consumer(n.output[0])
if consumer is not None and consumer.op_type == "Mul":
@@ -174,8 +175,11 @@ class Absorb1BitMulIntoMatMul(Transformation):
Wnew.shape == W.shape
), """Shape of new weights is not
the same as the shape of the weight matrix before."""
- model.set_initializer(matmul_weight_name, Wnew)
- n.output[0] = consumer.output[0]
- graph.node.remove(consumer)
- graph_modified = True
+ check_fxn = np.vectorize(lambda x: Wdt.allowed(x))
+ # only absorb if permitted by W datatype
+ if check_fxn(Wnew).all():
+ model.set_initializer(matmul_weight_name, Wnew)
+ n.output[0] = consumer.output[0]
+ graph.node.remove(consumer)
+ graph_modified = True
return (model, graph_modified)
diff --git a/tests/brevitas/test_brevitas_fc.py b/tests/brevitas/test_brevitas_fc.py
index 6be2c9a255ead2cd3f9cbcceaca60816060b19bf..db18d91e3590e896e111c9e38bdc4de43872a98c 100644
--- a/tests/brevitas/test_brevitas_fc.py
+++ b/tests/brevitas/test_brevitas_fc.py
@@ -45,13 +45,17 @@ from finn.util.test import get_test_model_trained
export_onnx_path = make_build_dir("test_brevitas_fc_")
-# activation: None or DataType
-@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
-# weight bits
-@pytest.mark.parametrize("wbits", [1])
# act bits
@pytest.mark.parametrize("abits", [1, 2])
+# weight bits
+@pytest.mark.parametrize("wbits", [1, 2])
+# network topology / size
+@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits):
+ if size == "LFC" and wbits == 2 and abits == 2:
+ pytest.skip("No LFC-w2a2 present at the moment")
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
new file mode 100644
index 0000000000000000000000000000000000000000..a2318d451c4e90c374405077c73e6878add49f2e
--- /dev/null
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -0,0 +1,297 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+from pkgutil import get_data
+
+import pytest
+
+import numpy as np
+
+# as of Feb'20 there is a bug that segfaults ONNX shape inference if we
+# import pytorch before onnx, so we make sure to import onnx first
+import onnx # NOQA
+import onnx.numpy_helper as nph
+
+import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
+from finn.core.modelwrapper import ModelWrapper
+from finn.core.onnx_exec import execute_onnx
+from finn.custom_op.registry import getCustomOp
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
+from finn.transformation.fpgadataflow.compile import Compile
+from finn.transformation.fpgadataflow.create_dataflow_partition import (
+ CreateDataflowPartition,
+)
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
+from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
+from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+ ReplaceVerilogRelPaths,
+)
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.synth_pynq_proj import SynthPYNQProject
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.infer_datatypes import InferDataTypes
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.streamline import Streamline
+from finn.util.basic import pynq_part_map
+from finn.util.test import get_test_model_trained
+
+build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
+test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
+test_fpga_part = pynq_part_map[test_pynq_board]
+target_clk_ns = 5
+
+
+def test_end2end_tfc_w2a2_export():
+ import brevitas.onnx as bo
+
+ tfc = get_test_model_trained("TFC", 2, 2)
+ bo.export_finn_onnx(
+ tfc, (1, 1, 28, 28), build_dir + "/end2end_tfc_w2a2_export.onnx"
+ )
+
+
+def test_end2end_tfc_w2a2_import_and_tidy():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_export.onnx")
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model = model.transform(InferDataTypes())
+ model.save(build_dir + "/end2end_tfc_w2a2_tidy.onnx")
+
+
+def test_end2end_tfc_w2a2_streamline():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_tidy.onnx")
+ model = model.transform(Streamline())
+ model.save(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+
+
+def test_end2end_tfc_w2a2_convert_to_hls_layers():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ # model = model.transform(ConvertBipolarMatMulToXnorPopcount())
+ # model = model.transform(absorb.AbsorbAddIntoMultiThreshold())
+ # model = model.transform(absorb.AbsorbMulIntoMultiThreshold())
+ # model = model.transform(RoundAndClipThresholds())
+ # model = model.transform(to_hls.InferBinaryStreamingFCLayer())
+ model = model.transform(to_hls.InferQuantizedStreamingFCLayer())
+ model.save(build_dir + "/end2end_tfc_w2a2_hls_layers.onnx")
+
+
+def test_end2end_tfc_w2a2_create_dataflow_partition():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_hls_layers.onnx")
+ parent_model = model.transform(CreateDataflowPartition())
+ parent_model.save(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ sdp_node = getCustomOp(parent_model.graph.node[2])
+ dataflow_model_filename = sdp_node.get_nodeattr("model")
+ dataflow_model = ModelWrapper(dataflow_model_filename)
+ dataflow_model.save(build_dir + "/end2end_tfc_w2a2_dataflow_model.onnx")
+
+
+def test_end2end_tfc_w2a2_fold_and_tlastmarker():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_model.onnx")
+ fc0 = model.graph.node[0]
+ fc1 = model.graph.node[1]
+ fc2 = model.graph.node[2]
+ fc3 = model.graph.node[3]
+ fc0w = getCustomOp(fc0)
+ fc1w = getCustomOp(fc1)
+ fc2w = getCustomOp(fc2)
+ fc3w = getCustomOp(fc3)
+ fc0w.set_nodeattr("inFIFODepth", 50)
+ fc0w.set_nodeattr("SIMD", 8)
+ fc0w.set_nodeattr("PE", 16)
+ fc0w.set_nodeattr("outFIFODepth", 4)
+ fc1w.set_nodeattr("SIMD", 16)
+ fc1w.set_nodeattr("PE", 16)
+ fc1w.set_nodeattr("outFIFODepth", 4)
+ fc2w.set_nodeattr("SIMD", 16)
+ fc2w.set_nodeattr("PE", 16)
+ fc2w.set_nodeattr("outFIFODepth", 4)
+ fc3w.set_nodeattr("SIMD", 16)
+ fc3w.set_nodeattr("PE", 10)
+ fc3w.set_nodeattr("outFIFODepth", 50)
+ model = model.transform(InsertTLastMarker())
+ model.save(build_dir + "/end2end_tfc_w2a2_folded.onnx")
+
+
+def test_end2end_tfc_w2a2_gen_hls_ip():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_folded.onnx")
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(HLSSynth_IPGen())
+ model.save(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
+
+
+def test_end2end_tfc_w2a2_ip_stitch():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+
+
+def test_end2end_tfc_w2a2_verify_dataflow_part():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+ x = np.zeros((1, 784), dtype=np.float32)
+ inp_name = model.graph.input[0].name
+ out_name = model.graph.output[0].name
+ inp_dict = {inp_name: x}
+ # npysim
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ model = model.transform(SetExecMode("npysim"))
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_npysim.onnx")
+ ret_npysim = execute_onnx(model, inp_dict, True)
+ res_npysim = ret_npysim[out_name]
+ # node-by-node rtlsim
+ model = model.transform(SetExecMode("rtlsim"))
+ getCustomOp(model.graph.node[0]).set_nodeattr("rtlsim_trace", "default")
+ getCustomOp(model.graph.node[1]).set_nodeattr("rtlsim_trace", "default")
+ getCustomOp(model.graph.node[2]).set_nodeattr("rtlsim_trace", "default")
+ getCustomOp(model.graph.node[3]).set_nodeattr("rtlsim_trace", "default")
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_nodebynode_rtlsim.onnx")
+ ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
+ res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
+ # whole-network (ip-stitched) rtlsim
+ model.set_metadata_prop("exec_mode", "rtlsim")
+ model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_whole_rtlsim.onnx")
+ ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
+ res_rtlsim_whole = ret_rtlsim_whole[out_name]
+ assert np.isclose(res_npysim, res_rtlsim_nodebynode).all()
+ assert np.isclose(res_npysim, res_rtlsim_whole).all()
+
+
+def test_end2end_tfc_w2a2_verify_all():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ raw_i = get_data("finn", "data/onnx/mnist-conv/test_data_set_0/input_0.pb")
+ input_tensor = onnx.load_tensor_from_string(raw_i)
+ x = nph.to_array(input_tensor)
+ # x = np.zeros(ishape, dtype=np.float32)
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ # produce results with npysim
+ sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w2a2_ipstitch_npysim.onnx")
+ ret_npysim = execute_onnx(parent_model, {iname: x}, True)
+ y_npysim = ret_npysim[oname]
+ # produce results with node-by-node rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_tfc_w2a2_ipstitch_nodebynode_rtlsim.onnx"
+ )
+ ret_nodebynode_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_nodebynode_rtlsim = ret_nodebynode_rtlsim[oname]
+ # produce results with whole-network (stitched ip) rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_tfc_w2a2_ipstitch_whole_rtlsim.onnx"
+ )
+ ret_whole_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_whole_rtlsim = ret_whole_rtlsim[oname]
+ assert np.isclose(y_golden, y_npysim).all()
+ assert np.isclose(y_golden, y_nodebynode_rtlsim).all()
+ assert np.isclose(y_golden, y_whole_rtlsim).all()
+
+
+def test_end2end_tfc_w2a2_make_pynq_proj():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+ model = model.transform(MakePYNQProject(test_pynq_board))
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
+
+
+def test_end2end_tfc_w2a2_synth_pynq_project():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
+ model = model.transform(SynthPYNQProject())
+ model.save(build_dir + "/end2end_tfc_w2a2_synth.onnx")
+
+
+def test_end2end_tfc_w2a2_make_driver():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_synth.onnx")
+ model = model.transform(MakePYNQDriver())
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_driver.onnx")
+
+
+def test_end2end_tfc_w2a2_deploy_on_pynq():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_pynq_driver.onnx")
+ try:
+ ip = os.environ["PYNQ_IP"] # no fault for this one; skip if not defined
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ username = os.getenv("PYNQ_USERNAME", "xilinx")
+ password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
+ model = model.transform(DeployToPYNQ(ip, username, password, target_dir))
+ # save the model to be able to link it to the parent
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_deploy.onnx")
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
+
+
+def test_end2end_tfc_w2a2_run_on_pynq():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ raw_i = get_data("finn", "data/onnx/mnist-conv/test_data_set_0/input_0.pb")
+ input_tensor = onnx.load_tensor_from_string(raw_i)
+ x = nph.to_array(input_tensor)
+ # x = np.zeros(ishape, dtype=np.float32)
+ # run using FINN-based execution
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ try:
+ ip = os.environ["PYNQ_IP"] # NOQA
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ # produce results with npysim
+ sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w2a2_pynq_deploy.onnx")
+ ret = execute_onnx(parent_model, {iname: x}, True)
+ y = ret[oname]
+ assert np.isclose(y, y_golden).all()
+
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py
index b287ab65265448983fcfe4f7d94d595cd5ac5343..c68561239b7c30973856fa282d20cd2afaa168ae 100644
--- a/tests/transformation/streamline/test_streamline_fc.py
+++ b/tests/transformation/streamline/test_streamline_fc.py
@@ -45,13 +45,17 @@ from finn.util.basic import make_build_dir
export_onnx_path = make_build_dir("test_streamline_fc_")
-# activation: None or DataType
-@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
-# weight bits
-@pytest.mark.parametrize("wbits", [1])
# act bits
@pytest.mark.parametrize("abits", [1, 2])
+# weight bits
+@pytest.mark.parametrize("wbits", [1, 2])
+# network topology / size
+@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
def test_streamline_fc(size, wbits, abits):
+ if size == "LFC" and wbits == 2 and abits == 2:
+ pytest.skip("No LFC-w2a2 present at the moment")
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)