From 17a76202ff3143f8767a4d0bbd93f16753c23fb5 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Wed, 1 Jun 2022 16:59:26 +0100
Subject: [PATCH] [CustomOps] Propagate cppsim output shapes to be reflected in
custom ops
---
.../custom_op/fpgadataflow/addstreams_batch.py | 8 +++-----
.../custom_op/fpgadataflow/channelwise_op_batch.py | 5 +----
.../fpgadataflow/convolutioninputgenerator.py | 6 ++----
.../fpgadataflow/convolutioninputgenerator1d.py | 6 ++----
src/finn/custom_op/fpgadataflow/downsampler.py | 6 ++----
.../fpgadataflow/duplicatestreams_batch.py | 14 ++++++++------
src/finn/custom_op/fpgadataflow/fmpadding_batch.py | 6 ++----
.../custom_op/fpgadataflow/globalaccpool_batch.py | 6 ++----
.../custom_op/fpgadataflow/labelselect_batch.py | 6 ++----
src/finn/custom_op/fpgadataflow/pool_batch.py | 6 ++----
.../fpgadataflow/streamingfclayer_batch.py | 7 ++-----
.../fpgadataflow/streamingmaxpool_batch.py | 6 ++----
.../fpgadataflow/vector_vector_activate_batch.py | 7 ++-----
13 files changed, 32 insertions(+), 57 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
index 7ba67247a..d1da1e0e5 100644
--- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
@@ -56,7 +56,7 @@ class AddStreams_Batch(HLSCustomOp):
my_attrs.update(super().get_nodeattr_types())
return my_attrs
- def get_normal_input_shape(self):
+ def get_normal_input_shape(self, ind=0):
ich = self.get_nodeattr("NumChannels")
vecs = list(self.get_nodeattr("numInputVectors"))
ishape = tuple(vecs + [ich])
@@ -166,7 +166,6 @@ class AddStreams_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -211,9 +210,8 @@ class AddStreams_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
index f6c562454..462b8b6e6 100644
--- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
+++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
@@ -431,11 +431,8 @@ class ChannelwiseOp_Batch(HLSCustomOp):
out = 2 * out - 1
context[node.output[0]] = out
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
+ context[node.output[0]].shape == self.get_normal_output_shape()
), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index e27b46b11..150c3b719 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -286,7 +286,6 @@ class ConvolutionInputGenerator(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -325,10 +324,9 @@ class ConvolutionInputGenerator(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
index 5cb9bce0c..b25246f1e 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
@@ -420,7 +420,6 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -459,10 +458,9 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py
index 789d6ece9..aa3bad9e4 100644
--- a/src/finn/custom_op/fpgadataflow/downsampler.py
+++ b/src/finn/custom_op/fpgadataflow/downsampler.py
@@ -264,7 +264,6 @@ class DownSampler(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -295,9 +294,8 @@ class DownSampler(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
index d6f9f3bd3..fb15b260e 100644
--- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
@@ -76,10 +76,14 @@ class DuplicateStreams_Batch(HLSCustomOp):
folded_ishape = tuple(vecs + [folds, pe])
return folded_ishape
- def get_normal_output_shape(self):
+ def get_normal_output_shape(self, ind=0):
+ # since the output shape of both out streams are the same
+ # return independently from index
return self.get_normal_input_shape()
- def get_folded_output_shape(self):
+ def get_folded_output_shape(self, ind=0):
+ # since the output shape of both out streams are the same
+ # return independently from index
return self.get_folded_input_shape()
def make_shape_compatible_op(self, model):
@@ -203,7 +207,6 @@ class DuplicateStreams_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
n_outputs = self.get_num_output_streams()
if mode == "cppsim":
@@ -237,10 +240,9 @@ class DuplicateStreams_Batch(HLSCustomOp):
)
for i in range(n_outputs):
assert (
- context[node.output[i]].shape == folded_oshape
+ context[node.output[i]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[i]] = context[node.output[i]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
index a2d42f63a..177ca2acb 100644
--- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
+++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
@@ -328,7 +328,6 @@ class FMPadding_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -359,9 +358,8 @@ class FMPadding_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
index 7812b9531..43a7dc211 100644
--- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
@@ -185,7 +185,6 @@ class GlobalAccPool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -215,10 +214,9 @@ class GlobalAccPool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
index da994fb13..bb83311da 100644
--- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py
+++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
@@ -182,7 +182,6 @@ class LabelSelect_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -212,10 +211,9 @@ class LabelSelect_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/pool_batch.py b/src/finn/custom_op/fpgadataflow/pool_batch.py
index 7d0ad4310..09d707ae2 100644
--- a/src/finn/custom_op/fpgadataflow/pool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/pool_batch.py
@@ -343,7 +343,6 @@ class Pool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
folded_ishape = self.get_folded_input_shape()
exp_oshape = self.get_normal_output_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -377,9 +376,8 @@ class Pool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 96a3139dc..2a47c8d80 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -954,11 +954,8 @@ class StreamingFCLayer_Batch(HLSCustomOp):
out = 2 * out - 1
context[node.output[0]] = out
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
- ), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
+ context[node.output[0]].shape == self.get_normal_output_shape()
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
index 6fbf176d4..b9c2350c0 100755
--- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
@@ -342,7 +342,6 @@ class StreamingMaxPool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -379,10 +378,9 @@ class StreamingMaxPool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py b/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
index 3d8dcaf2f..549b1724a 100644
--- a/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
+++ b/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
@@ -433,11 +433,8 @@ class Vector_Vector_Activate_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
- ), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
+ context[node.output[0]].shape == self.get_normal_output_shape()
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
--
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