diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
index 7ba67247a37b790eb14f12948613eb975105cd84..d1da1e0e524986332429079f79d36ae62f7cfd1e 100644
--- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
@@ -56,7 +56,7 @@ class AddStreams_Batch(HLSCustomOp):
my_attrs.update(super().get_nodeattr_types())
return my_attrs
- def get_normal_input_shape(self):
+ def get_normal_input_shape(self, ind=0):
ich = self.get_nodeattr("NumChannels")
vecs = list(self.get_nodeattr("numInputVectors"))
ishape = tuple(vecs + [ich])
@@ -166,7 +166,6 @@ class AddStreams_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -211,9 +210,8 @@ class AddStreams_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
index f6c5624543e47f488e5c42983a324ff48b43decd..462b8b6e6ec845b75e3594460807ccc7f37bbe9e 100644
--- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
+++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
@@ -431,11 +431,8 @@ class ChannelwiseOp_Batch(HLSCustomOp):
out = 2 * out - 1
context[node.output[0]] = out
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
+ context[node.output[0]].shape == self.get_normal_output_shape()
), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index e27b46b11ca43a804ea01571b0e1604e8e3e16a1..150c3b7198d139c29a342460bab499c73bb84196 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -286,7 +286,6 @@ class ConvolutionInputGenerator(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -325,10 +324,9 @@ class ConvolutionInputGenerator(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
index 5cb9bce0c86b6be533527a58ecbd8d08f82fa59b..b25246f1eaf73e14836bb6d00a5704f8bd3ce892 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
@@ -420,7 +420,6 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -459,10 +458,9 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py
index 789d6ece9ad1d8cfc16353b638df31a422cffb72..aa3bad9e41f78c3d6ae4bcd23d99bb7c4c72800c 100644
--- a/src/finn/custom_op/fpgadataflow/downsampler.py
+++ b/src/finn/custom_op/fpgadataflow/downsampler.py
@@ -264,7 +264,6 @@ class DownSampler(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -295,9 +294,8 @@ class DownSampler(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
index d6f9f3bd3baf7a2961e8fe4447a4f86a6458a664..fb15b260e6bdfd57f42e0e4659a1536bb716b526 100644
--- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
@@ -76,10 +76,14 @@ class DuplicateStreams_Batch(HLSCustomOp):
folded_ishape = tuple(vecs + [folds, pe])
return folded_ishape
- def get_normal_output_shape(self):
+ def get_normal_output_shape(self, ind=0):
+ # since the output shape of both out streams are the same
+ # return independently from index
return self.get_normal_input_shape()
- def get_folded_output_shape(self):
+ def get_folded_output_shape(self, ind=0):
+ # since the output shape of both out streams are the same
+ # return independently from index
return self.get_folded_input_shape()
def make_shape_compatible_op(self, model):
@@ -203,7 +207,6 @@ class DuplicateStreams_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
n_outputs = self.get_num_output_streams()
if mode == "cppsim":
@@ -237,10 +240,9 @@ class DuplicateStreams_Batch(HLSCustomOp):
)
for i in range(n_outputs):
assert (
- context[node.output[i]].shape == folded_oshape
+ context[node.output[i]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[i]] = context[node.output[i]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
index a2d42f63a8f5c9cf997ad540040daa21cb3d39d1..177ca2acbd60b49658a61741ec042e651b560b27 100644
--- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
+++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
@@ -328,7 +328,6 @@ class FMPadding_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -359,9 +358,8 @@ class FMPadding_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
index 7812b9531ed742ae00bb4383f5dc77c84c77f4c4..43a7dc211c0fe0689629cb9bb4d4b0664ac9eef9 100644
--- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
@@ -185,7 +185,6 @@ class GlobalAccPool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -215,10 +214,9 @@ class GlobalAccPool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
index da994fb13971e2066c9838b8c963372ab1ee0d92..bb83311dab44a4942d6bc1b581c21abb1e993493 100644
--- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py
+++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
@@ -182,7 +182,6 @@ class LabelSelect_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
if mode == "cppsim":
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
@@ -212,10 +211,9 @@ class LabelSelect_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected ofolded utput shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/pool_batch.py b/src/finn/custom_op/fpgadataflow/pool_batch.py
index 7d0ad43107d53168f441d1513c3855300cfdf4f8..09d707ae238a90b596f18400b58a6508f0413692 100644
--- a/src/finn/custom_op/fpgadataflow/pool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/pool_batch.py
@@ -343,7 +343,6 @@ class Pool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
folded_ishape = self.get_folded_input_shape()
exp_oshape = self.get_normal_output_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -377,9 +376,8 @@ class Pool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
- ), "cppsim did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ context[node.output[0]].shape == exp_oshape
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 96a3139dcffb83aaca0303546c49e5b8cf73424b..2a47c8d808e7427433d3e05dd6d29fc5e6f609a2 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -954,11 +954,8 @@ class StreamingFCLayer_Batch(HLSCustomOp):
out = 2 * out - 1
context[node.output[0]] = out
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
- ), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
+ context[node.output[0]].shape == self.get_normal_output_shape()
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
index 6fbf176d4c80d5b5cd6caac294e131ec1a515438..b9c2350c0c20035358780e90ddb6f2923d171af5 100755
--- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
@@ -342,7 +342,6 @@ class StreamingMaxPool_Batch(HLSCustomOp):
exp_ishape = self.get_normal_input_shape()
exp_oshape = self.get_normal_output_shape()
folded_ishape = self.get_folded_input_shape()
- folded_oshape = self.get_folded_output_shape()
# TODO ensure codegen dir exists
if mode == "cppsim":
@@ -379,10 +378,9 @@ class StreamingMaxPool_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == folded_oshape
+ context[node.output[0]].shape == exp_oshape
), "cppsim \
- did not produce expected folded output shape"
- context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
diff --git a/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py b/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
index 3d8dcaf2fca52b6c23b10322e0061b580807e0bc..549b1724a979ee700ed4ef66393d6a938997ff00 100644
--- a/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
+++ b/src/finn/custom_op/fpgadataflow/vector_vector_activate_batch.py
@@ -433,11 +433,8 @@ class Vector_Vector_Activate_Batch(HLSCustomOp):
# load output npy file
super().npy_to_dynamic_output(context)
assert (
- context[node.output[0]].shape == self.get_folded_output_shape()
- ), """Output shape is not as expected"""
- # reshape output to have expected shape
- oshape = self.get_normal_output_shape()
- context[node.output[0]] = context[node.output[0]].reshape(*oshape)
+ context[node.output[0]].shape == self.get_normal_output_shape()
+ ), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()