From 130c14627b420245f0735e0ebc665cedf1655e59 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 8 May 2020 00:36:50 +0100
Subject: [PATCH] [Refactor] rename CodeGen_ipgen to PrepareIP
---
.../finn/source_code/finn.transformation.fpgadataflow.rst | 2 +-
notebooks/end2end_example/cnv_end2end_example.ipynb | 4 ++--
notebooks/end2end_example/tfc_end2end_example.ipynb | 8 ++++----
.../analysis/fpgadataflow/hls_synth_res_estimation.py | 4 ++--
.../transformation/fpgadataflow/create_stitched_ip.py | 2 +-
src/finn/transformation/fpgadataflow/hlssynth_ipgen.py | 2 +-
.../fpgadataflow/{codegen_ipgen.py => prepare_ip.py} | 2 +-
tests/end2end/test_end2end_cnv_w1a1.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a1_throughput_test.py | 4 ++--
tests/end2end/test_end2end_tfc_w1a2.py | 4 ++--
tests/end2end/test_end2end_tfc_w2a2.py | 4 ++--
.../fpgadataflow/test_fpgadataflow_convinputgenerator.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_dwc.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_fclayer.py | 6 +++---
tests/fpgadataflow/test_fpgadataflow_fifo.py | 4 ++--
tests/fpgadataflow/test_fpgadataflow_ip_stitch.py | 4 ++--
tests/fpgadataflow/test_layer_streaming_maxpool_batch.py | 4 ++--
17 files changed, 33 insertions(+), 33 deletions(-)
rename src/finn/transformation/fpgadataflow/{codegen_ipgen.py => prepare_ip.py} (98%)
diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
index 0e0842898..e57314ea1 100644
--- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
@@ -16,7 +16,7 @@ finn.transformation.fpgadataflow.cleanup
finn.transformation.fpgadataflow.codegen\_ipgen
-----------------------------------------------
-.. automodule:: finn.transformation.fpgadataflow.codegen_ipgen
+.. automodule:: finn.transformation.fpgadataflow.prepare_ip
:members:
:undoc-members:
:show-inheritance:
diff --git a/notebooks/end2end_example/cnv_end2end_example.ipynb b/notebooks/end2end_example/cnv_end2end_example.ipynb
index d465e6afb..2c1e269a5 100644
--- a/notebooks/end2end_example/cnv_end2end_example.ipynb
+++ b/notebooks/end2end_example/cnv_end2end_example.ipynb
@@ -462,7 +462,7 @@
"metadata": {},
"outputs": [],
"source": [
- "from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen\n",
+ "from finn.transformation.fpgadataflow.prepare_ip import PrepareIP\n",
"from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen\n",
"from finn.util.basic import pynq_part_map\n",
"\n",
@@ -471,7 +471,7 @@
"target_clk_ns = 5\n",
"\n",
"model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_folded.onnx\")\n",
- "model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))\n",
+ "model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))\n",
"model = model.transform(HLSSynth_IPGen())\n",
"model.save(build_dir + \"/end2end_cnv_w1a1_ipgen.onnx\")"
]
diff --git a/notebooks/end2end_example/tfc_end2end_example.ipynb b/notebooks/end2end_example/tfc_end2end_example.ipynb
index b149bd0f3..83c7ec4a6 100644
--- a/notebooks/end2end_example/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_example.ipynb
@@ -948,10 +948,10 @@
"metadata": {},
"source": [
"Two transformations are required to generate HLS IP blocks for each layer: \n",
- "* `CodeGen_ipgen` which generates the HLS C++ code for the node and a tcl-script which starts the HLS synthesis and exports the design as IP. \n",
+ "* `PrepareIP` which generates the HLS C++ code for the node and a tcl-script which starts the HLS synthesis and exports the design as IP. \n",
"* `HLSSynth_IPGen` which passes the tcl-script to Vivado HLS and thus performs the actual IP generation. \n",
"\n",
- "We start off by giving unique node names using the basic transformation `GiveUniqueNodeNames`, and then proceed with the HLS C++ code generation with `CodeGen_ipgen`."
+ "We start off by giving unique node names using the basic transformation `GiveUniqueNodeNames`, and then proceed with the HLS C++ code generation with `PrepareIP`."
]
},
{
@@ -963,8 +963,8 @@
"model = ModelWrapper(build_dir+\"/tfc_w1_a1_set_folding_factors.onnx\")\n",
"model = model.transform(GiveUniqueNodeNames())\n",
"\n",
- "from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen\n",
- "model = model.transform(CodeGen_ipgen(fpga_part, target_clk_ns))"
+ "from finn.transformation.fpgadataflow.prepare_ip import PrepareIP\n",
+ "model = model.transform(PrepareIP(fpga_part, target_clk_ns))"
]
},
{
diff --git a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
index 78fc2ccfc..968e09263 100644
--- a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
+++ b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
@@ -54,7 +54,7 @@ def hls_synth_res_estimation(model):
if code_gen_dir == "":
warnings.warn(
"""Could not find report files, values will be set to zero
- for this node. Please run "CodeGen_ipgen" transformation and
+ for this node. Please run "PrepareIP" transformation and
"HLSSynth_IPGen" first to generate the report files"""
)
else:
@@ -71,7 +71,7 @@ def hls_synth_res_estimation(model):
else:
warnings.warn(
"""Could not find report files, values will be set to zero
- for this node. Please run "CodeGen_ipgen" transformation and
+ for this node. Please run "PrepareIP" transformation and
"HLSSynth_IPGen" first to generate the report files"""
)
return res_dict
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 848c2068d..c22a21ebd 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -37,7 +37,7 @@ from finn.custom_op.registry import getCustomOp
class CreateStitchedIP(Transformation):
"""Create a Vivado IP Block Design project from all the generated IPs of a
graph. All nodes in the graph must have the fpgadataflow backend attribute,
- and the CodeGen_ipgen transformation must have been previously run on
+ and the PrepareIP transformation must have been previously run on
the graph. The resulting block design is also packaged as IP. The
transformation gets the fpgapart as a string.
diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py b/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
index 2af623818..f895b81c2 100644
--- a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
+++ b/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
@@ -58,7 +58,7 @@ class HLSSynth_IPGen(NodeLocalTransformation):
inst.get_nodeattr("code_gen_dir_ipgen") != ""
), """Node
attribute "code_gen_dir_ipgen" is empty. Please run
- transformation CodeGen_ipgen first."""
+ transformation PrepareIP first."""
# call the compilation function for this node
inst.ipgen_singlenode_code()
# ensure that executable path is now set
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipgen.py b/src/finn/transformation/fpgadataflow/prepare_ip.py
similarity index 98%
rename from src/finn/transformation/fpgadataflow/codegen_ipgen.py
rename to src/finn/transformation/fpgadataflow/prepare_ip.py
index fa7725ae1..1e2062e3b 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipgen.py
+++ b/src/finn/transformation/fpgadataflow/prepare_ip.py
@@ -57,7 +57,7 @@ def _codegen_single_node(node, model, fpgapart, clk):
raise Exception("Custom op_type %s is currently not supported." % op_type)
-class CodeGen_ipgen(Transformation):
+class PrepareIP(Transformation):
"""Call custom implementation to generate code for single custom node
and create folder that contains all the generated files.
All nodes in the graph must have the fpgadataflow backend attribute and
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
index 802dd5acd..c8c8bc311 100644
--- a/tests/end2end/test_end2end_cnv_w1a1.py
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -55,7 +55,7 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import (
)
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
ReplaceVerilogRelPaths,
@@ -169,7 +169,7 @@ def test_end2end_cnv_w1a1_fold_and_tlastmarker():
def test_end2end_cnv_w1a1_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_folded.onnx")
- model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index 1829b9a9d..e413b7532 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -46,7 +46,7 @@ from finn.core.throughput_test import throughput_test
from finn.custom_op.registry import getCustomOp
from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
from finn.transformation.fold_constants import FoldConstants
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
@@ -155,7 +155,7 @@ def test_end2end_tfc_w1a1_fold_and_tlastmarker():
def test_end2end_tfc_w1a1_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_folded.onnx")
- model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index e8ce5612b..ec4d86295 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -43,7 +43,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
from finn.transformation.fold_constants import FoldConstants
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
@@ -147,7 +147,7 @@ def test_end2end_tfc_w1a2_fold_and_tlastmarker():
def test_end2end_tfc_w1a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_folded.onnx")
- model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
index cef14862b..7d0f0287e 100644
--- a/tests/end2end/test_end2end_tfc_w2a2.py
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -43,7 +43,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
from finn.transformation.fold_constants import FoldConstants
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
@@ -147,7 +147,7 @@ def test_end2end_tfc_w2a2_fold_and_tlastmarker():
def test_end2end_tfc_w2a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_folded.onnx")
- model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
index 99a69990b..46cc78e3d 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
@@ -33,7 +33,7 @@ from onnx import TensorProto, helper
import finn.core.onnx_exec as oxe
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
@@ -152,7 +152,7 @@ def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, exec_mode,
elif exec_mode == "rtlsim":
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
model = model.transform(PrepareRTLSim())
else:
diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py
index 146588183..0a35b7832 100644
--- a/tests/fpgadataflow/test_fpgadataflow_dwc.py
+++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py
@@ -4,7 +4,7 @@ from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
@@ -65,7 +65,7 @@ def test_fpgadataflow_dwc_rtlsim(Shape, INWidth, OUTWidth, finn_dtype):
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
model = model.transform(PrepareRTLSim())
y = oxe.execute_onnx(model, input_dict)["outp"]
diff --git a/tests/fpgadataflow/test_fpgadataflow_fclayer.py b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
index bcee86264..127053828 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fclayer.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
@@ -38,7 +38,7 @@ from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_es
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
from finn.custom_op.multithreshold import multithreshold
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
@@ -297,7 +297,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
# works for parametrized tests...
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
model = model.transform(ReplaceVerilogRelPaths())
model = model.transform(PrepareRTLSim())
@@ -389,7 +389,7 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode(
# works for parametrized tests...
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
model = model.transform(ReplaceVerilogRelPaths())
model = model.transform(PrepareRTLSim())
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
index 139ce3848..14efa0683 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fifo.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -5,7 +5,7 @@ from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
@@ -87,7 +87,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
model = model.transform(PrepareRTLSim())
y = oxe.execute_onnx(model, input_dict)["outp"]
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index 3d8e17d85..47352eeb9 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -37,7 +37,7 @@ from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
from finn.core.onnx_exec import execute_onnx
from finn.custom_op.registry import getCustomOp
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
@@ -208,7 +208,7 @@ def test_fpgadataflow_ipstitch_gen_model(): # exec_mode):
model.set_metadata_prop("exec_mode", "remote_pynq")
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen(test_fpga_part, 5))
+ model = model.transform(PrepareIP(test_fpga_part, 5))
model = model.transform(HLSSynth_IPGen())
assert model.graph.node[0].op_type == "StreamingFCLayer_Batch"
assert model.graph.node[-1].op_type == "TLastMarker"
diff --git a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
index 79a7cca30..a2a522b12 100644
--- a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
+++ b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
@@ -33,7 +33,7 @@ from onnx import TensorProto, helper
import finn.core.onnx_exec as oxe
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
-from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
@@ -143,7 +143,7 @@ def test_fpgadataflow_streamingmaxpool(idt, k, ifm_dim, ifm_ch, exec_mode):
elif exec_mode == "rtlsim":
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
model = model.transform(PrepareRTLSim())
else:
--
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