From 1237bb99a8f35498ff84236870fa5ba598dbdc3d Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sun, 16 Feb 2020 20:19:35 +0000
Subject: [PATCH] [IPStitch] add extra metadata prop for generated wrapper
---
src/finn/transformation/fpgadataflow/codegen_ipstitch.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
index 93408d6cf..a39b3c439 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
+++ b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
@@ -134,7 +134,9 @@ class CodeGen_ipstitch(Transformation):
)
bd_filename = "%s/%s.bd" % (bd_base, block_name)
tcl.append("make_wrapper -files [get_files %s] -top" % bd_filename)
- tcl.append("add_files -norecurse %s/hdl/%s_wrapper.v" % (bd_base, block_name))
+ wrapper_filename = "%s/hdl/%s_wrapper.v" % (bd_base, block_name)
+ tcl.append("add_files -norecurse %s" % wrapper_filename)
+ model.set_metadata_prop("wrapper_filename", wrapper_filename)
# export list of used Verilog files (for rtlsim later on)
tcl.append("set all_v_files [get_files -filter {FILE_TYPE == Verilog}]")
v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
--
GitLab