diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py
index d2e7ea6d71d00084cac0ed79de34e2df5f9bcb43..5f526aa2aa1917144c7a048c9d9314aa9288a2d8 100644
--- a/src/finn/custom_op/fpgadataflow/templates.py
+++ b/src/finn/custom_op/fpgadataflow/templates.py
@@ -101,6 +101,7 @@ set_part $config_proj_part
 
 config_interface -m_axi_addr64
 config_rtl -auto_prefix
+$EXTRA_DIRECTIVES$
 
 create_clock -period $config_clkperiod -name default
 csynth_design