From 0899ce44739f88cf290b5b22c12c72e9ddf33556 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 10 Jun 2020 16:49:17 +0100
Subject: [PATCH] [rtlsim] no autoeval for IP-stitched rtlsim
---
src/finn/core/rtlsim_exec.py | 21 ++++++++++++---------
src/finn/util/fpgadataflow.py | 1 +
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/finn/core/rtlsim_exec.py b/src/finn/core/rtlsim_exec.py
index e5e6d29bd..ad44dab57 100644
--- a/src/finn/core/rtlsim_exec.py
+++ b/src/finn/core/rtlsim_exec.py
@@ -86,9 +86,7 @@ def rtlsim_exec(model, execution_context):
sim = pyverilate_stitched_ip(model)
model.set_metadata_prop("rtlsim_so", sim.lib._name)
else:
- sim = PyVerilator(rtlsim_so)
- _reset_rtlsim(sim)
- _toggle_clk(sim)
+ sim = PyVerilator(rtlsim_so, auto_eval=False)
ret = _run_rtlsim(sim, packed_input, num_out_values, trace_file)
packed_output = ret[0]
model.set_metadata_prop("sim_cycles", str(ret[1]))
@@ -104,18 +102,22 @@ def _reset_rtlsim(sim):
"""Sets reset input in pyverilator to zero, toggles the clock and set it
back to one"""
sim.io.ap_rst_n_0 = 0
- sim.io.ap_clk_0 = 1
- sim.io.ap_clk_0 = 0
+ _toggle_clk(sim)
+ _toggle_clk(sim)
sim.io.ap_rst_n_0 = 1
+ _toggle_clk(sim)
+ _toggle_clk(sim)
def _toggle_clk(sim):
"""Toggles the clock input in pyverilator once."""
- sim.io.ap_clk_0 = 1
sim.io.ap_clk_0 = 0
+ sim.eval()
+ sim.io.ap_clk_0 = 1
+ sim.eval()
-def _run_rtlsim(sim, inp, num_out_values, trace_file=None):
+def _run_rtlsim(sim, inp, num_out_values, trace_file=None, reset=True):
"""Runs the pyverilator simulation by passing the input values to the simulation,
toggle the clock and observing the execution time. Argument num_out_values contains
the number of expected output values, so the simulation is closed after all
@@ -140,6 +142,8 @@ def _run_rtlsim(sim, inp, num_out_values, trace_file=None):
if trace_file is not None:
sim.start_vcd_trace(trace_file)
+ if reset:
+ _reset_rtlsim(sim)
while not (output_observed):
sim.io.in0_V_V_0_tvalid = 1 if len(inputs) > 0 else 0
@@ -148,8 +152,7 @@ def _run_rtlsim(sim, inp, num_out_values, trace_file=None):
inputs = inputs[1:]
if sim.io.out_r_0_tvalid == 1 and sim.io.out_r_0_tready == 1:
outputs = outputs + [sim.io.out_r_0_tdata]
- sim.io.ap_clk_0 = 1
- sim.io.ap_clk_0 = 0
+ _toggle_clk(sim)
observation_count = observation_count + 1
no_change_count = no_change_count + 1
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index d1669444e..3fe747a84 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -104,6 +104,7 @@ def pyverilate_stitched_ip(model):
build_dir=build_dir,
trace_depth=get_rtlsim_trace_depth(),
top_module_name=top_module_name,
+ auto_eval=False,
)
return sim
--
GitLab