From 047d95355734eefb84423d1432bbb21b26c11c44 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Wed, 13 May 2020 18:59:48 +0100
Subject: [PATCH] [Transform] set default Fclk to 10 ns
---
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 9b0a387c5..0e898f63d 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -49,7 +49,7 @@ class CreateStitchedIP(Transformation):
The packaged block design IP can be found under the ip subdirectory.
"""
- def __init__(self, fpgapart, clk_ns):
+ def __init__(self, fpgapart, clk_ns = 10.0):
super().__init__()
self.fpgapart = fpgapart
self.clk_ns = clk_ns
--
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