1. 18 Feb, 2019 1 commit
  2. 15 Feb, 2019 1 commit
  3. 14 Feb, 2019 8 commits
  4. 13 Feb, 2019 4 commits
  5. 12 Feb, 2019 3 commits
  6. 11 Feb, 2019 10 commits
  7. 10 Feb, 2019 3 commits
  8. 08 Feb, 2019 2 commits
  9. 07 Feb, 2019 3 commits
    • Jonatan Antoni's avatar
      CoreValidation: Fixed AC6 assembler and linker flags for Cortex-M targets. · 17c6b356
      Jonatan Antoni authored
      Change-Id: I8ad81ca7de91231c33c4d2c20948742d361e16ea
      17c6b356
    • Kevin Bracey's avatar
      RTX5: Add CLREX to exception exit paths · 647a940c
      Kevin Bracey authored
      Safe use of LDREX/STREX requires that any thread switches, interrupts or
      any other disruption between the LDREX and STREX be visible, so
      exception handlers must ensure that the exclusive monitor flag is clear
      when returning to foreground code.
      
      Two possible error cases are
      
         <thread 1>
         LDREX          exclusive monitor set
         <thread switch 2>
         STR            exclusive monitor cleared
         LDREX          exclusive monitor set
         <thread switch 1>
         STREX          !!! store succeeds because exclusive monitor set
      
      or
      
         <thread>
         LDREX          exclusive monitor set
         <IRQ>
         STR            exclusive monitor cleared
         LDREX          exclusive monitor set
         // No store because of failed compare-and-swap
         <IRQ return>
         STREX          !!! store succeeds because exclusive monitor set
      
      For ARMv7-M and ARMv8-A, the monitor is automatically cleared on
      exception return, but ARMv7-A requires that the clear be performed in
      software.
      
      Unneeded CLREX removed from data abort entry.  The entry state of the
      exclusive monitor may be unknown on entry to an exception handler, but
      no code can possibly be relying on it being clear - an STREX that is
      intended to store must be preceded by an LDREX.
      647a940c
    • Jonatan Antoni's avatar
      CoreValidation: Fixed AC5 compiler settings for CA5 targets. · 03b221f1
      Jonatan Antoni authored
      Change-Id: I68b68d8bfaf8be817bd1c3cf24bf4826c3ef915f
      03b221f1
  10. 06 Feb, 2019 5 commits