Const-qualify all read-only pointers in CMSIS-DSP (#349)

Change-Id: I1b397e953fdcbca9f82f5390ec39d2429c5ef8db

Running tests in non-secure mode needs different system partitioning than
running tests in secure mode, i.e. used interrupts needs to be assigned
to non-secure.

Change-Id: I4de29c4f4e22cc4bc86af1c92741bbf1b5625aa8

Added volatile keywords to make the instruction sequence less
dependent on the Compiler optimization level.

Change-Id: I60b23d0dd959e34a0cc8e0c798dc01ae88686494

On devices with NEON extensions compilers doing auto-vectorization leads
to the usage of VFP instruction for MMU setup. This needs the FPU to be
enabled at early stage.

Change-Id: I19b0f6e47248efcd86c3ae50e6c110bdebbf64cc

Change-Id: I5511a55e265e5e59b00c2aecf57df2c16332355a

Change-Id: I76937a782642672561c8698e73b38ab24b1262db

Change-Id: Ic2e722bb9e54bb6da7546955fa79d5f56adc0b21

RTX5: Add CLREX to exception exit paths

Fix incorrect pointer sign for arm_cfft_radix4_q15's bit reversal table (was signed, should be unsigned)

Change-Id: Id67d50ca7ec02da8ba4856a3f2bcc0a0cef49340

... with a proper error message.

Change-Id: I1e6ef40991cb8805add4c0b9a75a1149dcea5e57

Change-Id: I8ad81ca7de91231c33c4d2c20948742d361e16ea

Safe use of LDREX/STREX requires that any thread switches, interrupts or
any other disruption between the LDREX and STREX be visible, so
exception handlers must ensure that the exclusive monitor flag is clear
when returning to foreground code.

Two possible error cases are

   <thread 1>
   LDREX          exclusive monitor set
   <thread switch 2>
   STR            exclusive monitor cleared
   LDREX          exclusive monitor set
   <thread switch 1>
   STREX          !!! store succeeds because exclusive monitor set

or

   <thread>
   LDREX          exclusive monitor set
   <IRQ>
   STR            exclusive monitor cleared
   LDREX          exclusive monitor set
   // No store because of failed compare-and-swap
   <IRQ return>
   STREX          !!! store succeeds because exclusive monitor set

For ARMv7-M and ARMv8-A, the monitor is automatically cleared on
exception return, but ARMv7-A requires that the clear be performed in
software.

Unneeded CLREX removed from data abort entry.  The entry state of the
exclusive monitor may be unknown on entry to an exception handler, but
no code can possibly be relying on it being clear - an STREX that is
intended to store must be preceded by an LDREX.

Change-Id: I68b68d8bfaf8be817bd1c3cf24bf4826c3ef915f

Change-Id: Iaf2d7cc41eafac3c74987b02ceb0a64ceea5d37b

Change-Id: I56de604a5c8a2f5fd30accd398d2b7f84a001723

Change-Id: Ibfbb127994d51ed52c3c31614403a27abe1c21bc

Change-Id: Ic75fe7ef3164873475247f1615a3794d474dee98

RTX5: Make rtx_core_ca.h cope with compiler in Thumb mode