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- Fixed linter.py

Change-Id: I5a174ec423339d0ed029b07a393bf1f5819bfb6b

Change-Id: I556acb6dc6a8fc6157b48491ad1d60f66f709b45

- Added PMU events for Cortex-M55.
- Added PMU_Type and PMU define.
- Added missing core numbers to __CORTEX_M.
- Added missing SCB_InvalidateICache_by_Addr.
- Enhanced/reworked description of device config macros.

Change-Id: I3ebebe33dddbd2eddaea39a25cc268a106c9180b

Change-Id: If7ada5d8433176f56c42f25ce79aaad4b268da8e

- Added __VTOR_PRESENT to all VTOR-capable cores, defaulting to 1.
- Added __FPU_DP, __DCACHE_PRESENT and __ICACHE_PRESENT to Armv8.1-M cores.
- Updated defines to affected device headers.

Change-Id: I3e0c6a35e4b526b46c583566e2adc69d89b7020a

- SCB_InvalidateICache_by_Addr documentation added.
- osEventFlagsSet clarified behaviour when using osFlagsNoClear.
- osThreadFlagsSet clarified only target thread is affected.

Change-Id: Idc170670dad9e54739795d491a91ede6d2319c3f

Updating PMU Event Counter Number from 12 to 8 to align with Cortex-M55's default number when the PMU is configured.

Use __attribute*__*(..) rather than __attribute(..)

Change-Id: Ib92116ea8d4bad00b0b2277af156654ad9752ff8

ARM_SAI_ERROR_FRAME_LENG*HT* => ARM_SAI_ERROR_FRAME_LENG*TH*
Using @deprecated to notice the wrong one, and added the new.

Change-Id: Ieb4eb047752c29079baa810e88b879800d508921

When __ARM_FEATURE_MVE is defined the security settings for CP10/CP11
need to be set similar to FPU usage.

Change-Id: I3764698bcbbb038ac26b4fbc76590548b06b0863

Change-Id: I46df8a15ab4a43c69fa2f62bb7935f2129d6475c

This is a strainght port of the corresponding ARM examples.
The projects are setup to run on the simulator and teh default is an M3
target, but that can easily been changed after the example has been
imported.

The projects has been setup to use a simulated SysTick interrupt and the
thread viewer plugin.
Signed-off-by: TTornblom <thomas.tornblom@iar.com>

Aligned PMU function prototypes and definitions for PMU counter overflow and interrupt enable functions.
Fixed spacing issue with some comments.

Change-Id: I88dce50f659d6a4017ce640618adecb638b905cd

1. MVE support is added to depthwise_conv_s8_mult_4() for requantization.
2. CMSIS version is bumped up in ARM.CMSIS.pdsc

Change-Id: Ia80cf9830bfe7ac46302f107ceb4769903cdf134

- Fixed reserved numbering in PMU_Type struct
- Added missing PMU_BASE and PMU defines for CM55

Change-Id: I9583227a6e8904ad73b06a6e225c8096c1fb2053