Commit f53ee1dd authored by Reinhard Keil's avatar Reinhard Keil
Browse files

Added MPU for v8M, v8.1M

parent fbdea694
......@@ -765,6 +765,7 @@ INPUT = src/Overview.txt \
src/Ref_cm4_simd.txt \
src/Ref_FPU.txt \
src/Ref_MPU.txt \
src/Ref_MPU8.txt \
src/Ref_Systick.txt \
src/Ref_Debug.txt \
src/Ref_Trustzone.txt \
......
......@@ -37,7 +37,8 @@ Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMS
\section ref_v6-v8M Processor Support
CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.
CMSIS supports the complete range of <a href="https://developer.arm.com/products/processors/cortex-m" target="_blank"><b>Cortex-M processors</b></a> and
the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.
\subsection ref_man_sec Cortex-M Reference Manuals
......@@ -50,29 +51,37 @@ The Cortex-M Device Generic User Guides contain the programmers model and detail
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)
\if ARMv8M
The \b Cortex-M23 and \b Cortex-M33 are described with Technical Reference Manuals that are available here:
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)
\endif
\if ARMv8M \subsection ARMv8M Armv8-M Architecture
CMSIS also supports the following Cortex-M processor variants:
- <a href="https://developer.arm.com/products/processors/cortex-m/cortex-m1" target="_blank"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>Cortex-M35P</b></a> is a temper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
\subsection ARMv8M Armv8-M and Armv8.1-M Architecture
Armv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
Both Armv8-M profiles are supported by CMSIS.
Both Armv8-M profiles and Armv8.1M are supported by CMSIS.
The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.
The Armv8.1-M Architecture further extends Armv8-M with Helium, an Microcontroller Vector Extension (MVE) and further instruction set and debug extensions.
More information about Armv8.1-M Architecture is available under <a href="https://developer.arm.com/technologies/helium" target="_blank"><b>Arm Helium technology</b></a>.
\endif
<hr>
\section tested_tools_sec Tested and Verified Toolchains
\todo verify versions below
The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
- Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
- Arm: Arm Compiler 6.9
- Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
- Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23/33/35P, Armv8-M, Armv8.1-M)
- Arm: Arm Compiler 6.12
- Arm: Arm Compiler 6.6.2 (not for Cortex-M0/23/33/35P, Armv8-M, Armv8.1-M)
- GNU: GNU Tools for Arm Embedded 6.3.1 20170620
- IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
......@@ -92,6 +101,8 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
<td>V5.2.0</td>
<td>
Added: Cortex-M35P support.\n
Added: Cortex-M1 support.\n
Added: Armv8.1 architecture support.
</td>
</tr>
<tr>
......@@ -102,13 +113,13 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
Added support for Cortex-M1 (beta). \n
Removed usage of register keyword. \n
Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. \n
Enhanced MPUv7 API with defines for memory access attributes.\n
Enhanced MPUv7 API with defines for memory access attributes.
</td>
</tr>
<tr>
<td>V5.1.1</td>
<td>
Aligned MSPLIM and PSPLIM access functions along supported compilers.\n
Aligned MSPLIM and PSPLIM access functions along supported compilers.
</td>
</tr>
<tr>
......@@ -116,7 +127,7 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
<td>
Added MPU Functions for ARMv8-M for Cortex-M23/M33.\n
Moved __SSAT and __USAT intrinsics to CMSIS-Core.\n
Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.\n
Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.
</td>
</tr>
<tr>
......
/**
\defgroup mpu_functions MPU Functions for Armv7-M
\defgroup mpu_functions MPU Functions for Armv6-M/v7-M
\brief Functions that relate to the Memory Protection Unit.
\details
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.
......
/**
\defgroup mpu8_functions MPU Functions for Armv8-M
\brief Functions that relate to the Memory Protection Unit.
\details
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.
The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.
<b>Example:</b>
\code
void main()
{
// Set Region 0
ARM_MPU_SetRegionEx(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));
ARM_MPU_Enable(0);
// Execute application code that is access protected by the MPU
ARM_MPU_Disable();
}
\endcode
@{
*/
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I)
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP)
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \param XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
#if !defined(MPU_RLAR_PXN_Pos) || !defined(MPU_RLAR_PXN_Msk)
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX)
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control);
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void);
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE ARM_MPU_Enable_NS(uint32_t MPU_Control)
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void);
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr);
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr);
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr);
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr);
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr);
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr);
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar);
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len);
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
/** @} */
......@@ -3,8 +3,8 @@
*/
/**
\defgroup trustzone_functions TrustZone for Armv8-M
\brief Functions that related to optional Armv8-M security extension
\defgroup trustzone_functions TrustZone for Armv8-M/v8.1-M
\brief Functions that related to optional Armv8-M and Armv8.1-M security extension
@{
\details
The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology.
......
......@@ -14,6 +14,14 @@ The header file <b>cmsis_version.h</b> is included by each core header so that t
#error We need CMSIS 5.1 or later!
#endif
\endcode
<b>Deprecated</b>
The following macros are deprecated:
- \b __XXX_CMSIS_VERSION_MAIN which is replaced by \ref __CM_CMSIS_VERSION_MAIN.
- \b __XXX_CMSIS_VERSION_SUB which is replaced by \ref __CM_CMSIS_VERSION_SUB.
- \b __XXX_CMSIS_VERSION which is replaced by \ref __CM_CMSIS_VERSION.
@{
*/
......@@ -40,6 +48,7 @@ The header file <b>cmsis_version.h</b> is included by each core header so that t
\details This define can be used to differentiate between the various available Cortex-M controllers.
Possible values are:
- 0 for a Cortex-M0 or Cortex-M0+
- 1 for a Cortex-M1
- 3 for a Cortex-M3
- 4 for a Cortex-M4
- 7 for a Cortex-M7
......@@ -88,54 +97,6 @@ This define is only available for Cortex Secure Core controllers.
\endcond
*/
/**
\defgroup version_control_depricated_gr Version Control per Core (Depricated)
\brief Version \#define symbols for CMSIS release specific C/C++ source code
\details
Prior CMSIS release 5.1.0 the version information was core specific.
<b>Code Example:</b>
\code
#if !defined(__CM_CMSIS_VERSION) && defined(__CORTEX_M)
#if ((__CORTEX_M == 0) && (__CM0_CMSIS_VERSION >= 0x00050000)) || \
((__CORTEX_M == 3) && (__CM3_CMSIS_VERSION >= 0x00050000)) || \
((__CORTEX_M == 4) && (__CM4_CMSIS_VERSION >= 0x00050000)) || \
((__CORTEX_M == 7) && (__CM7_CMSIS_VERSION >= 0x00050000))
#error Yes, we have CMSIS 5!
#else
#error We need CMSIS 5!
#endif
#else
#error We need a Cortex-M controller!
#endif
\endcode
@{
*/
/**
\brief Contains the CMSIS major version for core of type XXX, i.e. CM0 or SC300.
\details The CMSIS major version can be used to differentiate between CMSIS major releases.
\deprecated Only rely on this define for CMSIS 5.0 and before.
*/
#define __XXX_CMSIS_VERSION_MAIN
/**
\brief Contains the CMSIS minor version for core of type XXX, i.e. CM0 or SC300.
\details The CMSIS minor version can be used to query a CMSIS release update level.
\deprecated Only rely on this define for CMSIS 5.0 and before.
*/
#define __XXX_CMSIS_VERSION_SUB
/**
\brief Contains the CMSIS version for core of type XXX, i.e. CM0 or SC300.
\details The CMSIS version is a combination of the \ref __CM_CMSIS_VERSION_MAIN (bits 31..15) and \ref __CM_CMSIS_VERSION_SUB (bits 14..0).
\deprecated Only rely on this define for CMSIS 5.0 and before.
*/
#define __XXX_CMSIS_VERSION
/**
@}
*/
/**
@}
......
......@@ -38,7 +38,7 @@ PROJECT_NAME = "CMSIS-Zone (Preview)"
# could be handy for archiving the generated documentation or if some version
# control system is used.
PROJECT_NUMBER = "Version 0.0.1"
PROJECT_NUMBER = "Version 0.9.0"
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
......
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