Pack: Update PDSC and changelogs for 5.3.0 release.

ARM.CMSIS.pdsc

@@ -8,17 +8,12 @@
   <url>http://www.keil.com/pack/</url>
 
   <releases>
-    <release version="5.2.1-dev4">
-       Active development...
-    </release>
-    <release version="5.2.1-dev3" date="2018-01-23">
-       CMSIS-NN: 1.0.0
+    <release version="5.3.0-rc0" date="2018-02-20">
+      Updated Arm company brand.
+      CMSIS-Core(M): 5.1.1 (see revision history for details)
+      CMSIS-Core(A): 1.1.1 (see revision history for details)
+      CMSIS-NN: 1.0.0
         - Initial contribution of the bare metal Neural Network Library.
-    </release>
-    <release version="5.2.1-dev2">
-       Updated company brand.
-    </release>
-    <release version="5.2.1-dev1">
       CMSIS-RTOS2:
         - RTX 5.3.0 (see revision history for details)
         - OS Tick API 1.0.1
@@ -32,7 +27,7 @@
         - Added additional access functions for physical timer.
       CMSIS-DAP: 1.2.0 (see revision history for details)
       CMSIS-DSP: 1.5.2 (see revision history for details)
-      CMSIS-Driver 2.6.0(see revision history for details):
+      CMSIS-Driver: 2.6.0 (see revision history for details)
         - CAN Driver API V1.2.0
         - NAND Driver API V2.3.0
       CMSIS-RTOS:
@@ -2072,7 +2067,7 @@ and 8-bit Java bytecodes in Jazelle state.
 
   <components>
     <!-- CMSIS-Core component -->
-    <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.0.2"  condition="ARMv6_7_8-M Device" >
+    <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.1"  condition="ARMv6_7_8-M Device" >
       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
       <files>
         <!-- CPU independent -->
@@ -2085,7 +2080,7 @@ and 8-bit Java bytecodes in Jazelle state.
       </files>
     </component>
 
-    <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.0.1"  condition="ARMv7-A Device" >
+    <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.1"  condition="ARMv7-A Device" >
       <description>CMSIS-CORE for Cortex-A</description>
       <files>
         <!-- CPU independent -->

CMSIS/DoxyGen/Core/core.dxy

@@ -38,7 +38,7 @@ PROJECT_NAME           = "CMSIS-Core (Cortex-M)"
 # could be handy for archiving the generated documentation or if some version
 # control system is used.
 
-PROJECT_NUMBER         = "Version 5.1.0"
+PROJECT_NUMBER         = "Version 5.1.1"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a

CMSIS/DoxyGen/Core/src/Overview.txt

@@ -82,6 +82,12 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
       <th>Version</th>
       <th>Description</th>
     </tr>
+    <tr>
+      <td>V5.1.1</td>
+      <td>
+        Aligned MSPLIM and PSPLIM access functions along supported compilers.\n
+      </td>
+    </tr>
     <tr>
       <td>V5.1.0</td>
       <td>

CMSIS/DoxyGen/Core_A/core_A.dxy

@@ -38,7 +38,7 @@ PROJECT_NAME           = "CMSIS-Core (Cortex-A)"
 # could be handy for archiving the generated documentation or if some version
 # control system is used.
 
-PROJECT_NUMBER         = "Version 1.1.0"
+PROJECT_NUMBER         = "Version 1.1.1"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a

CMSIS/DoxyGen/Core_A/src/Overview.txt

@@ -66,6 +66,14 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
       <th>Version</th>
       <th>Description</th>
     </tr>
+    <tr>
+      <td>V1.1.1</td>
+      <td>
+        <ul>
+          <li>Refactored L1 cache maintenance to be compiler agnostic.</li>
+        </ul>
+      </td>
+    </tr>
     <tr>
       <td>V1.1.0</td>
       <td>

CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt

@@ -165,6 +165,12 @@ File/Folder                  | Content
       <td>
        - Added Object Memory usage counters.
        - Added support for additional external configuration file.
+       - Added user configurable names for system threads (Idle and Timer).
+       - Added support for OS sections when using ARMCC5.
+       - Added callback for MPU integration (experimental)
+       - Increased default thread stack sizes to 256 bytes.
+       - Fixed stack context display for running thread in SCVD.
+       - Enhanced MISRA Compliance.
       </td>
     </tr>
     <tr>

README.md

 # CMSIS Version 5
 
-The branch *master* of this GitHub repository contains the CMSIS Version 5.2.0.  The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
+The branch *master* of this GitHub repository contains the CMSIS Version 5.3.0.  The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
 
 Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5.