Core(M): Fixed ARM_MPU_Disable barriers. (#458)

Change-Id: Ia8b10728563f8591816745c9490e1598aecc1978

CMSIS/Core/Include/mpu_armv7.h

@@ -202,8 +202,7 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif

CMSIS/Core/Include/mpu_armv8.h

@@ -141,8 +141,7 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
@@ -167,8 +166,7 @@ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
 */
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif